hi masters. this faq is very helpful. i need help!!! i'am currently doing verification of the zdut made in VHDL. i need to prepare testplan before i start. so if i get an idea how to make a testplan would be very helpfull. for example. i need to test a FIFO. this is just to make me understand. but i have to verify more complex designs. so if any one out here, can help me with this, keeping an FIFO as an example would be very greatfull. thanks Abbs...
- posted
17 years ago