Field-Programmable Gate Arrays

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initializing array of registers in XST

Steve, Peter and Austin- Can you give definitive instructions -- or point me to who can -- for initializing an array of...
5 comments posted 20yrs
posted by jbrower
5 comments posted 20yrs posted by jbrower

Xilinx SystemACE on multi-FPGA board

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 OK, Xilinx was uniquely unhelpful this time, so I resort to this list. My...
4 comments posted 20yrs
posted by spamtrap
4 comments posted 20yrs posted by spamtrap

Development Platform for begginer

Hi, I've got a little knowledge about fpga's. I've used for fun spartan2 at school. I'm interested in embedded systems...
4 comments posted 20yrs
posted by gburx
4 comments posted 20yrs posted by gburx

System Generator

Does any buddy knows what are the steps to bring a system generator model in to VHDL top level module. I have a simple...
0 comments posted 20yrs
posted by fpgalearner
0 comments posted 20yrs posted by fpgalearner

CLock Issue

Hi, If i have 100 MHz clock how can i generate a 200 Hz with 50% duty cycle clock. Let me explain why i need this.... I...
6 comments posted 20yrs
posted by fpgalearner
6 comments posted 20yrs posted by fpgalearner

LED Driver

Hi, We would like to drive LEDs using Ramp Waveforms using Xilinx CPLDs. Is it possible to write a driver and control th...
6 comments posted 20yrs
posted by pavithra.eswaran
6 comments posted 20yrs posted by pavithra.eswaran

UCF-mode for Emacs

Since I couldn't find a good mode file for editing Xilinx User Constraint File (UCF) in Emacs, I put one together. This...
2 comments posted 20yrs
posted by jimwu88NOOOSPAM
2 comments posted 20yrs posted by jimwu88NOOOSPAM

How are constants stored ?

Hello all, I always wondered the following: How are constants implemented in an FPGA ? How many can be stored without c...
9 comments posted 20yrs
posted by rover8898
9 comments posted 20yrs posted by rover8898

Xilinx PCI 64/32 bits IP

Hello, We have a design with master PCI DMA in 64 bits. This design implements the xilinx PCI 64/32 bits IP. The proble...
4 comments posted 20yrs
posted by t
4 comments posted 20yrs posted by t

Modelsim Simulation

I have a mismatch in Modelsim behavioral simulations using 1) VHDL testbench in ISE and 2) manual entry of stimuli. Whi...
1 comments posted 20yrs
posted by yaseenzaidi
1 comments posted 20yrs posted by yaseenzaidi

OpenRisc 1200 on a XUP

Has anyone implemented OR1K on a XUP?
1 comments posted 20yrs
posted by karrelsj
1 comments posted 20yrs posted by karrelsj

The use of analog switches as level translators

At least Analog Devices and also Fairchild propose analog switches as level translators to interface eg 1.8V logic to 3...
2 comments posted 20yrs
posted by none
2 comments posted 20yrs posted by none