the OP asked about using Xilinx Platform Cable for SPI programming, not about altermatives.
purchasing jtagkey for 139EUR (what ist just a box with ft2232c+lever shifter) just to program an SPI flash only because Xilinx is doing so bad with the support of their own cables in not so much an option.
Xilinx USB platform cable could of course theoretically do spi programming as it it based on Cypress FX2 + upgradeable CPLD, but xilinx is doing a bad job with the support of the cables. All the xilinx SPI support seems to be done by some students, that would explain why there is no support for USB platform cable, as such support would require update for the usb platform cable and that info is was possible not available for those who wrote the XSPI thing.
Too bad - the Xilinx USB cable is quite nice piece of hardware but its so closed design, that it well of course it could be reprorammed to be Altera Byteblaste :) - firmware for this is now under GPL and available (sure the PLD should be updated as well to be plain bypass)
sorry for ranting - but I have had to mess up with some boards that are using Xilinx CPLD+spi solution and are supposed to be programmed with the xilinx SPI tool. And that experiences is just another 2 weeks of my time wasted in frustration.
Xilinx - please dont get upset (again) - I say what I think, and I cant (and dont wanna) change that.
For the Xilinx Platform Cable issues there is a very elegant solution - no work at required from Xilinx just a matter of making a decision - so here it comes:
IDEA for Xilinx
-------------------- Open up the Platform USB Cable design in such manner that it could be used by 3rd parties, eg the Cable would still start and configure as it normally does but afterwards a secondary protocol could be used to reload new firmware and re-enumarate as new device with new host drivers.
All that is needed from Xilinx is the decison that such use is OK and some small bits of information - all the rest would be done by the community
- of course, everything that happens with the cable after the secondary protocol is no longer under Xilinx control meaning that there is no support required from Xilinx. This would allow the cable to be used as SPI programmer or any some other gadget as required.