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please help me out

hey friends , I'm trying to design an interface between a ps2 keyboard and the digilent DIO5 board which contains a Xilinx CoolRunner CPLD.

but the Xilinx synthesis tool Xst drove me crazy here are the errors I got followed by my VHDL code please help me

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit ... =========================================================================

  • Final Report *

here is my code

--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity kbd is port(
	kclk,kd,uclk : in std_logic; -- keyboard clk , keyboard data ,
universal clk ,respectively
	s_ca: out std_logic_vector(7 downto 0);	-- seven-segments display
	s_an: out std_logic_vector(3 downto 0)-- seven-segments anode
);
end kbd;

--}} End of automatically maintained section

architecture kbd_archi of kbd is


signal ready : std_logic := '1'; -- 11 bits have been received
signal data : std_logic_vector(7 downto 0);	  -- ASCCI character
pressed
constant keyup : std_logic_vector := x"f0"; -- keyup character
signal dr : std_logic_vector(10 downto 0); -- a temporary register to
hold the data coming from the kbd
signal count : std_logic_vector(1 downto 0) := "00"; -- to indicate
that the key up has been received and expecting the final data
signal ssg : std_logic_vector(7 downto 0);	-- seven-segments temp.
register
begin

p1 : process(kclk)
subtype int is integer range 0 to 11;
variable cnt : int := 0;
begin
	if falling_edge(kclk) then
		if cnt /= 11 then
		dr(cnt)
Reply to
Lovely Robot
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I noticed that both "P1" and "P2" processes assign a value to "ready". I'm surprised that ISE didn't complain about that. It looks like you meant process "P2" to be a counter. However, you didn't supply a clock, so "count

Reply to
Dave Pollum

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