Field-Programmable Gate Arrays

Routing problem in PAR.

Hello all, I am doing a design with block RAM. The register block is part of the full design which is causing concern....

2 comments posted 20yrs

posted by vssumesh_asic

2 comments posted 20yrs posted by vssumesh_asic

Interrupt signal sampling (Level or edge?)

Hi, What is the fair criteria for sampling the interrupt signal? For high priority critical interrupts and low priority...

6 comments posted 20yrs

posted by ashish.shringarpure

6 comments posted 20yrs posted by ashish.shringarpure

Altera Max Plus II to Quartus migration tool

I have a fairly large Altera-based design that will soon be updated to Cyclone II and Quartus (from Flex10K and Max+II)...

4 comments posted 20yrs

posted by e_s_p_i_a_n_

4 comments posted 20yrs posted by e_s_p_i_a_n_

simulation works fine but the actual chip doesnt work

Hi all, I am working on a chip design, where the frontend is interfaced to PCI bus and the backend has asynchronous FIF...

6 comments posted 20yrs

posted by sandeepbabel

6 comments posted 20yrs posted by sandeepbabel

constraints for DDR bus with 133MHz write and 66Mhz read clocks

I'm working on a design that needs to be able to write to a DDR ram at 133MHz but only needs to read back the data at a...

3 comments posted 20yrs

posted by dc

3 comments posted 20yrs posted by dc

ml-403 and USB

Has anyone used USB from linux on the ml-403 board? I'd like to get some peripherals like usb memory or bluetooth adapt...

1 comments posted 20yrs

posted by someone

1 comments posted 20yrs posted by someone

TME Free Verilog/VHDL framework generation tool

As a table based edit tool for HDL module's interface definition, Topweaver Module Editor (TME) unifies the process of...

0 comments posted 20yrs

posted by topweaver

0 comments posted 20yrs posted by topweaver

Xilinx ISE 8.1 Makefile

Hi, I am wondering if there is anyone who has worked out a way to use ISE 8.1 projects with Makefiles to compile FPGA i...

7 comments posted 20yrs

posted by jayasanka.piyaratna

7 comments posted 20yrs posted by jayasanka.piyaratna

Using vector condition at transition in StateCAD

Hi, I'm trying to use statecad to build a state machine diagram. There is a vector condition for changing from one state...

0 comments posted 20yrs

posted by tanceqi

0 comments posted 20yrs posted by tanceqi

help me to about clock in fpga

respected knowledgious persons, i want to know about how to give clock to fpga.as i know do we give it by software or h...

3 comments posted 20yrs

posted by kapilaryan2003

3 comments posted 20yrs posted by kapilaryan2003

Chipscope and FPGA

Hello everybody ! I'm using an fpga card with a PCMCIA format connexion : The link : http://www.annapmicro.com/wildcard...

1 comments posted 20yrs

posted by christophe.lucarz

1 comments posted 20yrs posted by christophe.lucarz

Crossing clock domains

Hi newsgroup, I have observed a strange behaviour in our VHDL design: One signal goes low and stays low (133MHz clock d...

7 comments posted 20yrs

posted by ALuPin

7 comments posted 20yrs posted by ALuPin

UK source for Digilent S3 board?

Anyone know a UK stockist for the Xilinx/Digilent S3 board ? (or anyone have a spare one - I only want the PCB) Xilinx...

2 comments posted 20yrs

posted by mike

2 comments posted 20yrs posted by mike

Putting the Ring into Ring oscillators

This news is interesting http://www.eet.com/news/latest/showArticle.jhtml?articleID=187200783&pgno=2 You do need a hype...

8 comments posted 20yrs

posted by no.spam

8 comments posted 20yrs posted by no.spam

PCI Express and DMA

I am looking for some assistance writing a driver and FPGA code to handle DMA on a PCI Express system. The FPGA is a Xi...

9 comments posted 20yrs

posted by songdrgn

9 comments posted 20yrs posted by songdrgn