Latest threads in Field-Programmable Gate Arrays

Unable to debug MicroBlaze in SDK (Eclipse) and the Software debugger

When I try to debug a program in eclipse the console sais :No source file named main.c. (This message appears 5 time an...

0 20yrs

raybakk

0 20yrs raybakk

Routing problem in PAR.

Hello all, I am doing a design with block RAM. The register block is part of the full design which is causing concern....

2 20yrs

vssumesh_asic

2 20yrs vssumesh_asic

Interrupt signal sampling (Level or edge?)

Hi, What is the fair criteria for sampling the interrupt signal? For high priority critical interrupts and low priority...

6 20yrs

ashish.shringarpure

6 20yrs ashish.shringarpure

Altera Max Plus II to Quartus migration tool

I have a fairly large Altera-based design that will soon be updated to Cyclone II and Quartus (from Flex10K and Max+II)...

4 20yrs

e_s_p_i_a_n_

4 20yrs e_s_p_i_a_n_

simulation works fine but the actual chip doesnt work

Hi all, I am working on a chip design, where the frontend is interfaced to PCI bus and the backend has asynchronous FIF...

6 20yrs

sandeepbabel

6 20yrs sandeepbabel

constraints for DDR bus with 133MHz write and 66Mhz read clocks

I'm working on a design that needs to be able to write to a DDR ram at 133MHz but only needs to read back the data at a...

3 20yrs

dc

3 20yrs dc

ml-403 and USB

Has anyone used USB from linux on the ml-403 board? I'd like to get some peripherals like usb memory or bluetooth adapt...

1 20yrs

someone

1 20yrs someone

TME Free Verilog/VHDL framework generation tool

As a table based edit tool for HDL module's interface definition, Topweaver Module Editor (TME) unifies the process of...

0 20yrs

topweaver

0 20yrs topweaver

Xilinx ISE 8.1 Makefile

Hi, I am wondering if there is anyone who has worked out a way to use ISE 8.1 projects with Makefiles to compile FPGA i...

7 20yrs

jayasanka.piyaratna

7 20yrs jayasanka.piyaratna

Using vector condition at transition in StateCAD

Hi, I'm trying to use statecad to build a state machine diagram. There is a vector condition for changing from one state...

0 20yrs

tanceqi

0 20yrs tanceqi

help me to about clock in fpga

respected knowledgious persons, i want to know about how to give clock to fpga.as i know do we give it by software or h...

3 20yrs

kapilaryan2003

3 20yrs kapilaryan2003

Chipscope and FPGA

Hello everybody ! I'm using an fpga card with a PCMCIA format connexion : The link : http://www.annapmicro.com/wildcard...

1 20yrs

christophe.lucarz

1 20yrs christophe.lucarz

Crossing clock domains

Hi newsgroup, I have observed a strange behaviour in our VHDL design: One signal goes low and stays low (133MHz clock d...

7 20yrs

ALuPin

7 20yrs ALuPin

UK source for Digilent S3 board?

Anyone know a UK stockist for the Xilinx/Digilent S3 board ? (or anyone have a spare one - I only want the PCB) Xilinx...

2 20yrs

mike

2 20yrs mike

Putting the Ring into Ring oscillators

This news is interesting http://www.eet.com/news/latest/showArticle.jhtml?articleID=187200783&pgno=2 You do need a hype...

8 20yrs

no.spam

8 20yrs no.spam

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