TME Free Verilog/VHDL framework generation tool

As a table based edit tool for HDL module's interface definition, Topweaver Module Editor (TME) unifies the process of HDL coding and document writing.

In a chip design process, for example ASIC or FPGA, people usually first plan the project on a top-down flow, then write the HDL code to implement the idea. However due to the restriction of traditional development tools, people are needed to code from the very bottom, which means a bottom-up coding style. This conflict between the plan and coding often brings to huge human labor and unreliable product quality. When finish coding, engineers always find the original project plan out-of-date and need rewriting. Topweaver Module Editor wants to change this situation.

With the tools from Topweaver family, people can quickly build the HDL code's framework, simultaneously with the document file. TME will be integrated into the next major version of Topweaver.

Features Unify the document and the HDL code with a powerful table based edit environment Full function table editor to simplify the human labor Generate HDL ports definition on Verilog95, Verilog2001 and VHDL Visually adjustment of HDL code format Support complex HDL code template HDL code synchronization enable secure modifications on existed design Extensible interface library to manage common used signals

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