Field-Programmable Gate Arrays

Programming the JTAG flash in circuit

We have a Xilinx Flash (XCF series I believe) that we would like to program in circuit from a microcontroller in order...

3 comments posted 20yrs

posted by wpiman

3 comments posted 20yrs posted by wpiman

Installing BFM toolkit

Dear All, Can anybody tell me what I have to do to install the BFM toolkit? When I follow the link "BFM Toolkit Install...

3 comments posted 20yrs

posted by jmariano

3 comments posted 20yrs posted by jmariano

Strange power up issue on Virtex4

Hi all, Our PCB is showing a strange start-up/configuration issue. The board has a virtex4 fpga (xc4vsx35-11) which giv...

9 comments posted 20yrs

posted by zeemanbe

9 comments posted 20yrs posted by zeemanbe

PCI Core compatibility

Hello i would like to know if anyone is familiar with any pci vendor core? I have 2 PCI core working on specific mother...

3 comments posted 20yrs

posted by krbyxtrm

3 comments posted 20yrs posted by krbyxtrm

booting problem ML300 :eth0: Could not read PHY control register; err

Hi all, I am loading linux onto the ML300. I have created a zImage.elf file for ppc with the drivers and bsps for the p...

4 comments posted 20yrs

posted by narashimanc

4 comments posted 20yrs posted by narashimanc

Can an FPGA be operated reliably in a car wheel?

What are the maximum g forces an FPGA could operate under? E.g. an FPGA sitting in a car wheel, where the car is travel...

43 comments posted 20yrs

posted by andrew.newsgroup

43 comments posted 20yrs posted by andrew.newsgroup

Funky experiment on a Spartan II FPGA

Hi all, I am trying to do a novel kind of experiment using a spartan II FPGA. I want to measure the impedence profile (...

19 comments posted 20yrs

posted by ankur101

19 comments posted 20yrs posted by ankur101

The differences between behaviors of 'std_logic_vector' and 'unsigned'

Hi, Based on suggestions from this group, when switching libraries from USE ieee.std_logic_1164.all; use ieee.std_logic...

2 comments posted 20yrs

posted by wtxwtx

2 comments posted 20yrs posted by wtxwtx

EDIFParser in JHDL / EDIF simulator?

Hi, all, sorry if the question appears stupid, I just want to get it start. also sorry about my poor english(it isn't m...

0 comments posted 20yrs

posted by yiqihuang

0 comments posted 20yrs posted by yiqihuang

A constant value of 0 in block

I have trouble during "Low Level Synthesis" of my code. It gets me following warings: WARNING:Xst:1989 - Unit : instanc...

3 comments posted 20yrs

posted by yiqihuang

3 comments posted 20yrs posted by yiqihuang

FPGA implementation of an OFDM-based modem

Hi all. As part of my university studies, I am involved in a university project concerning the analysis and design of a...

0 comments posted 20yrs

posted by nie

0 comments posted 20yrs posted by nie

flashing a led

I have a little problem with flashing a led. I want flash a led for indicating the status of my program. I do the follow...

8 comments posted 20yrs

posted by Laurent.George

8 comments posted 20yrs posted by Laurent.George

Spartan 3e starter kit & Multimedia

I just received my Spartan 3e starter kit and had to share my frustration... The huge DRAM and the fast FPGA seem to ma...

9 comments posted 20yrs

posted by beiermann

9 comments posted 20yrs posted by beiermann

FPGA-based hardware accelerator for PC

If one wanted to develop an FPGA-based hardware accelerator that could attach to the average PC to process data stored...

32 comments posted 20yrs

posted by lists

32 comments posted 20yrs posted by lists

Anyone use Xilinx ppc405 profiling tools?

Does anyone use the profiling tools with the Xilinx ppc405? I am trying to profile code on the ppc405 in a Xilinx XC2VP...

9 comments posted 20yrs

posted by alan

9 comments posted 20yrs posted by alan