Field-Programmable Gate Arrays

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altera cyclone memory example

Hi Everyone, I am a student trying to build a project with Altera's Cyclone FPGA board. For my project, I need to acces...
7 comments posted 20yrs
posted by roiavidan
7 comments posted 20yrs posted by roiavidan

ISE 7.1 synthesis problems

Hi all, I'm trying to synthesize a design using ISE 7.1 and am getting segmentation faults. The .srp file only gives me...
1 comments posted 20yrs
posted by hkannan
1 comments posted 20yrs posted by hkannan

ISE 7.1 segmentation faults

Hi all, I'm synthesizing a design using Xilinx ISE 7.1 and I get the following error message: make: *** [leon3mp.ngc] S...
0 comments posted 20yrs
posted by hkannan
0 comments posted 20yrs posted by hkannan

Synchronous Scrambler

Does anyone know of any good papers describing methods and or algorithms for implementing a Synchronous Scrambler (LFSR)...
3 comments posted 20yrs
posted by colinhankins
3 comments posted 20yrs posted by colinhankins

How to decide Fanout limit?

Hi, In Synplify Pro, there is a 'Fanout Guide' option. What is the reasonable value for this option? How to decide the...
8 comments posted 20yrs
posted by g.shrinivasan
8 comments posted 20yrs posted by g.shrinivasan

difference of variable and signal

What's the different between variable and signal? variable signal assignment operator: :=
6 comments posted 20yrs
posted by yiqihuang
6 comments posted 20yrs posted by yiqihuang

How to check IOB register packing?

Hi, I am using the "syn_useioff = 1" directive in my top module to pack the Input/Output registers into the IOB and syn...
11 comments posted 20yrs
posted by g.shrinivasan
11 comments posted 20yrs posted by g.shrinivasan

clock multiplier in spartan 2

how to implement a clock multiplier in spartan2 from ref clock. I have input clock of 25 mhz and need to generate 50 Mhz...
4 comments posted 20yrs
posted by ashish.shringarpure
4 comments posted 20yrs posted by ashish.shringarpure

JTAG tutorial

I created a small tutorial about JTAG. See http://www.fpga4fun.com/JTAG.html I'd be happy to hear about mistakes/suggest...
7 comments posted 20yrs
posted by jean.nicolle
7 comments posted 20yrs posted by jean.nicolle

Multiple Write Port Register Files

I'm working on a project that needs four write ports in a number of different register files. I'm already aware of time...
3 comments posted 20yrs
posted by lvalenty
3 comments posted 20yrs posted by lvalenty

ISE 8.1 error, help. Or where is the path?

I get this error when synthesising: ERROR:HDLParsers:3338 - "H:\Projektmapp\DENEX_LCS90_R2_V2\VHDL\TEST\fisa_vhdl.prj"...
2 comments posted 20yrs
posted by someone
2 comments posted 20yrs posted by someone

ISE 8.1 error, help

I get this error when synthesising: ERROR:HDLParsers:3338 - "H:\Projektmapp\DENEX_LCS90_R2_V2\VHDL\TEST\fisa_vhdl.prj"...
0 comments posted 20yrs
posted by someone
0 comments posted 20yrs posted by someone