Field-Programmable Gate Arrays

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MicroBlaze GPIO 1-bit [resistor], funny story :)

Hi A design engineer asked me if it should be ok to have an 1-bit GPIO in MicroBlaze design, well yes I answered - afte...
0 comments posted 20yrs
posted by Antti.Lukats
0 comments posted 20yrs posted by Antti.Lukats

sqrt(a^2 + b^2) in synthesizable VHDL?

How do i calculate sqrt(a^2 + b^2) in synthesizable VHDL? The signals a and b are 32 bit signed fix point numbers (std_l...
11 comments posted 20yrs
posted by someone
11 comments posted 20yrs posted by someone

XCFxxP Plaform Flash Device Questions

Hi, Was wondering if anyone has used the XCFxxP devices with revision selection controlled via the internal REVSEL bits...
4 comments posted 20yrs
posted by markm
4 comments posted 20yrs posted by markm

How can I deal with the output signal in testbech?

hello: I have a small count design, which I want to do functional simlation in modelsim. the code are following; module...
1 comments posted 20yrs
posted by springzzz
1 comments posted 20yrs posted by springzzz

reverse engineering ?

is it easy to reverse engineer ASIC/FPGA ? do u have any reference for this ?
33 comments posted 20yrs
posted by navarajci
33 comments posted 20yrs posted by navarajci

Xilinx warning for DCM

Hi, I am using a DCM in VirtexII which takes a 20 Mhz input and generates a 60 Mhz output. I am synthesizing using Synp...
2 comments posted 20yrs
posted by g.shrinivasan
2 comments posted 20yrs posted by g.shrinivasan

Altera Equiv.

I have a question for those experienced with Altera devices. Could someone please identify (roughly) the Brand A equivi...
5 comments posted 20yrs
posted by emh203
5 comments posted 20yrs posted by emh203

CoolRunner XPLA3 getting axed?

Is the coolrunner XPLA3 getting axed? I noticed that it is no longer a link on the xilinx font page. The online store d...
27 comments posted 20yrs
posted by emh203
27 comments posted 20yrs posted by emh203

Quartus II 6.0 available

Quartus II 6.0 is now available, I downloaded the Web Edition yesterday. I'm on the Altera mailing list but I don't rem...
4 comments posted 20yrs
posted by leon.heller
4 comments posted 20yrs posted by leon.heller

EDIF simulator???

Is there any good EDIF simulator around? I need to use it in my project. It will be good if it is free/cheap
0 comments posted 20yrs
posted by yiqihuang
0 comments posted 20yrs posted by yiqihuang

jhdlbits: source files

Ciao a tutti sono uno studente di ingengeria informatica, vorrei avere informazioni a rigurdo del progetto JHDLBITS, qu...
0 comments posted 20yrs
posted by happy_pippo81
0 comments posted 20yrs posted by happy_pippo81