Field-Programmable Gate Arrays

sending multiple char on RS232

Hi, I am trying to connect my Spartan 3 borad with PC by RS232 , and am able to echo single input in hyper temial conso...

10 comments posted 20yrs

posted by yiqihuang

10 comments posted 20yrs posted by yiqihuang

I can't connect to my Spartan 3 !!! ( Digilent starter kit )

I use Impact 8.1 When I want to download files on my starter kit, ( with the Digilent JTAG cable) Impact prompt this :...

1 comments posted 20yrs

posted by romaingoron

1 comments posted 20yrs posted by romaingoron

WARNING:iMPACT:923 - Can not find cable, check cable setup !

Hi ! I'm a newbie in FPGA ( and i'm french,that's why my english is not goo ). I have the Digilent Spartan 3 Starter ki...

2 comments posted 20yrs

posted by romaingoron

2 comments posted 20yrs posted by romaingoron

Xilinx or Altera...

Has anyone implemented DDR2 333Mhz (667Mbps) using Altera or Xilinx FPGA's Thanks

10 comments posted 20yrs

posted by sannuyaro

10 comments posted 20yrs posted by sannuyaro

requirements to select FPGA using LVDS

hi all, wat all the basic requirements needed to be analysed before selecting a FPGA chip for using high speed LVDS. tha...

2 comments posted 20yrs

posted by praveen.sethuram

2 comments posted 20yrs posted by praveen.sethuram

Synplify Pro warning - cudnt understand

Hi, In my TOP level verilog module, I have a data going from the ROM in one of the blocks to the input of the Multiplie...

0 comments posted 20yrs

posted by g.shrinivasan

0 comments posted 20yrs posted by g.shrinivasan

Actel Fusion FPGAs

I read a couple of threads on the Actel Fusion FPGAs from early this year saying they were delayed and not to expect th...

9 comments posted 20yrs

posted by spamgoeshere4

9 comments posted 20yrs posted by spamgoeshere4

USB2 camera to Xilinx ML40x boards

Does any one have any software (or experience) to share (or sell) concerning bringing a USB2 camera image into a XILINX...

7 comments posted 20yrs

posted by bradsmallridge

7 comments posted 20yrs posted by bradsmallridge

Microblaze dcm_module problems

I am trying to increase the clock frequency of my microblaze processor (currently 50 MHz) using the dcm_module frequenc...

2 comments posted 20yrs

posted by andrew.hood

2 comments posted 20yrs posted by andrew.hood

Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement

Hi everybody, I recently bought a Xilinx Spartan-3E evaluation board, which comes with an integrated Platform Cable USB...

39 comments posted 20yrs

posted by laurent.pinchart

39 comments posted 20yrs posted by laurent.pinchart

New Virtex4 Project, CoreGen

I want to instantiate some CoreGen modules to get some usage estimates on some possible target platforms. I've never cr...

0 comments posted 20yrs

posted by killerhertz

0 comments posted 20yrs posted by killerhertz

Xilinx XC4000 series

I have just been ask to upgrade an old product which uses a XC4010 and a 4005. I know that these parts are not supporte...

1 comments posted 20yrs

posted by paul.lowson

1 comments posted 20yrs posted by paul.lowson

Need help with old Xilinx project

I am looking for someone who can help me with an old design. THis was done with a XC4005 and of course none of the new...

0 comments posted 20yrs

posted by paul.lowson

0 comments posted 20yrs posted by paul.lowson

uClinux on MicroBlaze: Can't ping now

Hi everyone, I've followed the instructions from John Williams and Jason Wu, and finally got uClinux-kernel booted on m...

0 comments posted 20yrs

posted by qichen.huang

0 comments posted 20yrs posted by qichen.huang

Virtex 5 announced

Two slices per CLB, four 6-LUTs + 4 FFs per slice. A LUT can be configured as a RAM64 or SRL32. But a CLB can only have...

84 comments posted 20yrs

posted by ryanrs

84 comments posted 20yrs posted by ryanrs