Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Virtex 5 announced

Two slices per CLB, four 6-LUTs + 4 FFs per slice. A LUT can be configured as a RAM64 or SRL32. But a CLB can only have...
84 comments posted 20yrs
posted by ryanrs
84 comments posted 20yrs posted by ryanrs

IEEE-1394 (aka FireWire) Core

I am interested in any FPGA cores that implement the IEEE-1394a FireWire interface. The application is to process image...
7 comments posted 20yrs
posted by soar2morrow
7 comments posted 20yrs posted by soar2morrow

pull-ups and jtag questions

Hi, I have to establish a 50MHz serial communication with a Spartan3, so: 1) should I place termination resistors on da...
4 comments posted 20yrs
posted by marco
4 comments posted 20yrs posted by marco

Make a signal free for glitches?

I have a CPU register block where I use the outputs (wich are supposed to be static) to control other clock domains. Th...
11 comments posted 20yrs
posted by mleikvol
11 comments posted 20yrs posted by mleikvol

safety critical applications with FPGAs/CPLDs

Is there information available about projects using FPGAs/CPLDs successfully in safety critical application (e.g. autom...
3 comments posted 20yrs
posted by salewski
3 comments posted 20yrs posted by salewski

How to decide Setup/Hold time values ?

Hi, I am using Viretx II as my target FPGA. I use Synplify Pro 8.4 for synthesis and Xilinx ISE 7.1 for PAR. All my inp...
2 comments posted 20yrs
posted by g.shrinivasan
2 comments posted 20yrs posted by g.shrinivasan

getting good deals on small qty?

Hello, I am going to buy about five Spartan3 XC3S100Es along with config ROMs in the next few days. I may be ordering s...
19 comments posted 20yrs
posted by shawnn
19 comments posted 20yrs posted by shawnn

Floating point reality check

H have recently been working on a floating point unit for a Virtex 4 SX 35. I have a floating point adder and a floatin...
5 comments posted 20yrs
posted by ehliar
5 comments posted 20yrs posted by ehliar

Amontec Komodo board ?

Hi all ! Do you if we can find the schematics and other spec, of the "viewable version" on the website ? Like, price, Io...
2 comments posted 20yrs
posted by xavier.tastet
2 comments posted 20yrs posted by xavier.tastet

Raggedstone IO bracket ?

Hi All ! I saw on the web site lots of add-on, but is there "soon available" a kind of IO rear bracket to fit in the pc...
2 comments posted 20yrs
posted by xavier.tastet
2 comments posted 20yrs posted by xavier.tastet

Spartan 3E

I plan to use a Spartan3E device, namely XC3S500E-4PQG208C, in my next project, but there are several questions I would...
11 comments posted 20yrs
posted by wyderski
11 comments posted 20yrs posted by wyderski

Picture frame

Hi I'm new to fpga.. I do not have any dev-kit yet I'm looking for a fpga application to build a high res picture frame...
0 comments posted 20yrs
posted by wiljan
0 comments posted 20yrs posted by wiljan

filter design

hi everyone!! i designed a fir filter with the Xinlinx ipcore two days ago. and i am facing a problem! in my design, i...
1 comments posted 20yrs
posted by linhaidu840329
1 comments posted 20yrs posted by linhaidu840329

Trouble understanding Synplicity timing report

I'm having a problem understanding a Synplicity timing report. For the input ports of the design, the report gives colu...
1 comments posted 20yrs
posted by jd1033
1 comments posted 20yrs posted by jd1033