Field-Programmable Gate Arrays

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Re: ERROR:HDLCompilers:27 -

>unable to solve this error.I tried all the thing and check that there is no duplicate module..still its giving error.....
0 comments posted 12yrs
posted by 84408
0 comments posted 12yrs posted by 84408

Spartan 3 JTAG problems

Has anyone come across an issue where an XC3S200 is recognised in Impact; "Right Click to Add Device or Initialize JTAG...
2 comments posted 12yrs
posted by spam
2 comments posted 12yrs posted by spam

Nexys 4 FPGA Board

Hi all I'm usinf Digilent Nexys 4 FPGA BOard and I won't to run LInux kernel on microblaze and I don't have a lot of in...
0 comments posted 12yrs
posted by marwen.brikcha
0 comments posted 12yrs posted by marwen.brikcha

how to specify which feature for a license

Hi everyone, we have a license server that hosts both ACTEL_SUMMIT feature (1 seat) and ACTEL_VISTA one (10 seats). Is...
0 comments posted 12yrs
posted by al.basili
0 comments posted 12yrs posted by al.basili

Help: Altera megafunctions, Quartus II

I'm an FPGA newbie, working with the freeware Altera Quartus II IDE. I used the megafunction builder to create a FIFO m...
3 comments posted 12yrs
posted by bv
3 comments posted 12yrs posted by bv

more than 58'000 false paths...

Hi everyone, I started adding false paths to my design (see this thread for a context: ) but in order to avoid funny na...
10 comments posted 12yrs
posted by al.basili
10 comments posted 12yrs posted by al.basili

Actel Designer on multiple cores

Hi everyone, I had my vbox running with one core only (out of 4 on the host) and Designer was running extremely slow, s...
3 comments posted 12yrs
posted by al.basili
3 comments posted 12yrs posted by al.basili

synplify_pro check constraints in batch mode

Hi everyone, how can you perform a 'check constraints' run in batch mode with synplify pro? Background: I'm trying to s...
0 comments posted 12yrs
posted by al.basili
0 comments posted 12yrs posted by al.basili

[cross-post] group on systemC language

Hi everyone, does anyone out there know a group specialized on systemc? I'm interested in tlm modeling and platform vir...
7 comments posted 12yrs
posted by al.basili
7 comments posted 12yrs posted by al.basili

Re: Soft-Cores processors

Hi Makni, makni wrote: [] > I found a three Microblaze clones(aeMB, MB Lite and OpenFire) but I don't > know how to int...
0 comments posted 12yrs
posted by al.basili
0 comments posted 12yrs posted by al.basili

on-chip bypass caps

I got a spreadsheet from Altera that lists the on-chip power supply bypass caps on an Arria II GX95 FPGA. I was kind of...
25 comments posted 12yrs
posted by jlarkin
25 comments posted 12yrs posted by jlarkin

static timing analysis

Hi everyone, any good reference on STA? I know roughly well the principles but I've always wanted to get a deeper under...
1 comments posted 12yrs
posted by al.basili
1 comments posted 12yrs posted by al.basili

Tristates in synthesis

How well can the synthesis tools deal with tristates? If I use the following Verilog code for a Xilinx CPLD, with t as...
9 comments posted 12yrs
posted by pkk
9 comments posted 12yrs posted by pkk

Digilent Drivers stuck with Fedora 20

OK, I know Fedora 20 is not officially suported .... But, the install goes through just fine. I don't see any errors, I...
0 comments posted 12yrs
posted by rudolf.usselmann
0 comments posted 12yrs posted by rudolf.usselmann