TITLE Implementation of CCSDS based Telemetry Encoder on FPGA OBJECTIVES Design and development of CCSDS based Telemetry Encoder on FPGA using VHDL, for satellite applications. OUTLINE The project will comprise of three phases. First phase will be the know how development of CCSDS Packet TM encoding Standard. The second phase will be the implementation of all layers of standard on FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed. Finally all the modules will be integrated as a system in the third phase of the project. Complete working TM Encoder will be demonstrated on FPGA kit. MAJOR EQUIPMENT & SOFTWARE REQUIRED
Hardware: FPGA kit (Spartan-3 or Virtex) Software: Xilinx ISE
If this is any kind of school project - I'm not interested ( no way). I'm not going to take it for 100$. My time is much more expensive. If this is space application for serius client ( like NASA or something ) and is interesting , "beam me up Scotty".
I am pretty sure Nasa already has in-house CCSDS cores, for any other smaller space company I believe they can get the ESA CCSDS VHDL design (for free?) under a license agreement.
I also believe (but haven't checked as I no longer work in the space industry) that you can get most CCSDS modules (turbo codecs excluded?) from Gaisler research.
But here's the thing: university projects are assigned assuming that YOU will do the work. If you pay someone else to do the work and pass it off as yours, then that's cheating. You won't learn how to be a productive engineer by cheating (engineers actually have to use the knowledge they gain at school), you'll just get a piece of paper that says you are.
When you try to get an actual job and are asked to DO the things that you should have learned getting your degree, you'll fail. Then you'll either get fired, or you'll get made into a manager. You won't be a good manager -- you'll be a horrid manager. You'll be the kind of manager who cheats his boss (which makes his employees look bad), and cheats his employees (which makes them look bad), and generally makes life hell for every honest person within his event horizon.
I think I'm speaking for most of us here when I say that we take a very dim view of cheating. Even those of us who are amoral enough to not care about the actual cheating don't want to have to work under the kind of manager who cheats his way through school because he can't or won't do engineering. Since engineers tend to think in the long term, that means that we're not interested in a little bit of money today to foster a worse work environment for the rest of your life.
Now, if you want to actually DO the work, and all you want is some help to understand HOW to do the work (because god knows, not every professor is created equal, and some of them couldn't teach their way out of a paper bag), then by all means change your approach to "I've been assigned this project, and I need help figuring out how to get it done".
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Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
So , sorry then. I can help you in some difficult points if you give me right questions. If you cannot even start with this project - it is not for you. I completely agree with Tim. You should start with information what kind of project is it.
@Tim @Adam then i need some help regarding my project the help is that .... we just encode telemetry or on the Other Hand Packet telemetry encoder listed 8 thing ....
The Packet Telemetry Encoder (PTME) VHDL model comprises several encoders a nd modulators implementing the Consultative Committee for Space Data System s (CCSDS) recommendations and the European Space Agency (ESA) Procedures, S tandards and Specifications (PSS) for telemetry and channel coding. The Pa cket Telemetry Encoder (PTME) VHDL model comprises the following:
Telemetry Encoder (TME)
Reed-Solomon Encoder (RSE)
Turbo Encoder (TE)
Pseudo-Randomiser (PSR)
Non-Return-to-Zero Mark encoder (NRZ)
Convolutional Encoder (CE)
Split-Phase Level modulator (SP)
Clock Divider (CD) we encode just Telemetry encoder or all of the other encoder i'm confuse
Like Tom said, you need to ask your prof. This is a pretty good simulation of engineering in the real world: your boss, or a customer, or Sales, or whoever, will ask you to do something in general terms that turn out to be ambiguous. You need to deliver something very specific, so it's your job to take that English-language (or whatever language) and translate it into Engineering-English.
You want to do this BEFORE you've spent much time on actual design -- because any time spent designing the wrong thing is just time wasted.
The whole list of things there would be a pretty daunting task for one student to undertake as a project. It's not totally undoable, but I would hope that your prof is thinking more along the lines of having you build a piece of it, either to go onto something that someone else has done, or to serve as a foundation for someone else's work.
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Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Do you expect from me ( us ) answer to this question ? In my opinion it is lot of work if you going to implement all of them. Only RSE is big enough for you I think.
rs and modulators implementing the Consultative Committee for Space Data Sy stems (CCSDS) recommendations and the European Space Agency (ESA) Procedure s, Standards and Specifications (PSS) for telemetry and channel coding. Th e Packet Telemetry Encoder (PTME) VHDL model comprises the following:
@adam @tim you both are right ,,but something really interesting fact that you don't k now . the fact is that my Supervisor is not command from these kinds of topic....
so after your some solid reason ... here just one question is asked to u ... the question is.................. implement only one telemetry encoder
7OSI model layer i think only implement on telemetry encoder and other encoder don't use 7OSI layer model because The second phase will be the implementation of all layers of standard on FP GA using the VHDL language. Each layer will be implemented as a separate mo dule and simulation will be performed.
what can you suggest for me ???Please just Technical help for both of you
Hans (Tiggeler) has gave you an excellent overview of what exactly is avail able regarding CCSDS Telemetry Encoder IP.
I am interested in helping you (I provide paid support).
So if this is an academic exercise, and plagiarism is not tolerated o_O the n someone has to start from the specs (either directly you or the contracte e).
Do you have a deadline and budget to see if this is feasible?
Best regards Nikolaos Kavvadias
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ders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations and the European Space Agency (ESA) Procedu res, Standards and Specifications (PSS) for telemetry and channel coding. The Packet Telemetry Encoder (PTME) VHDL model comprises the following:
know .
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FPGA using the VHDL language. Each layer will be implemented as a separate module and simulation will be performed.
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