JTAG issues Cyclone V SoC

I am designing my own Altera Cyclone V SoM board. It is not intended to be a dev board. It will be a function module that also includes Analog Devices' SHARC DSPs.

I am working on the JTAG connection strategy. It seems to me that separate JTAG connections make more sense than chaining since Quartus may be running separately from the ARM (HPS).

Unless someone tells me something different, my plan is to use a pair of 2mm 2x5 headers, one for the FPGA and the other for the HPS. These would be identical to the Altera pinouts, just smaller.

I expect that the board will be running uLinux, probably GCC.

Here are my questions:

  1. I know that many of the Altera Cyclone V dev boards use a USB Blaster 2 circuit. Does anyone sell a USB Blaster 2 download cable? I have lots of USB Blaster clones already.

  1. What should I do about the HPS TRST#. It is not supported on the USB Blaster?

  2. The HPS Trace connections might be useful but these are needed for their alternate I/O functions. I am assuming that the Mictor interface will not be that helpful.

I would appreciate any other comments or insight.

Al

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Reply to
Al Clark
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I'd say take a schematic piece from a development kit and copy that. Original USB Blasters are sold from various distributors, however I've used a chinese clone and original one. Basically I see no difference between chinese and original one.

P.S. Disable that AVAST advertise.

Reply to
Tomas D.

"Tomas D." wrote in news:lj699g$td2$ snipped-for-privacy@dont-email.me:

Thanks Tomas for your comments.

I too have found that the clone USB Blasters are fine. The USB Blaster II uses high speed, not full speed USB. I have also noticed that pin 6 & pin 8 sometimes have alternate functions like warm reset and TRST#. I don't know if these are supported in the USB Blaster II.

I have been reviewing a variety of dev kit schematics for ideas.

On my design I used a pair of 2x5 2mm headers. I will make an adapter that will optionally allow chaining. I may break out to a mictor header as well as a 2x5 0.100 style Altera header.

I just changed an AVAST setting. Hopefully, the AVAST tag disappears with this post. I don't like it either.

Al

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Reply to
Al Clark

The standard 11Mbps USB Blaster is essentially an FT245 USB-to-parallel converter chip followed by a small CPLD doing parallel to serial conversion. Pins 6 and 8 are extra 'GPIOs' from the FT245 - they get used for doing other non-JTAG modes like Active Serial. They're not needed for standard FPGA programming.

The USB2 USB Blaster II uses a Cypress USB microcontroller instead of an FT245. Usually it's integrated onto boards. I've not seen it for sale as a separate device, though there are manuals dated Jan 2014 for it so it must exist. It looks like it's fairly new since it says it's only fully supported in Quartus 14.0 (USB2 support on other boards has existed for the last 2 years or so).

Note that some boards have an additional high-speed link for System Console

- this requires an extra bus from the FPGA into the Blaster CPLD: it won't work for a standalone JTAG programmer (but you can use System Console over slower JTAG instead).

The manual for the standalone Blaster II:

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shows that it does wire all the pins for Active Serial mode. My guess would be that the 'USB Interface Chip' is the Cypress FX2 microcontroller as there isn't a USB2 version of the FT245. That being so, don't expect clones anytime soon until someone duplicates the software.

Theo

Reply to
Theo Markettos

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