Latest threads in Field-Programmable Gate Arrays

PLB transfers: PPC to IP

I have a piece of IP that acts as a slave on the PLB. I would like writes to this IP to be 64bits, while reads from it...

1 20yrs

joeylrios

1 20yrs joeylrios

Need help reattaching top to FPGA

We had the top pop off of a VirtexII-Pro 2vp70 (1704BGA) and need to reattach it. The board and FPGA work fine. For som...

3 20yrs

mdini

3 20yrs mdini

PCI Design

hi, what is the difference for designing a PCI card for a desktop motherboard and with a Single Board Computer(SBC)? sho...

3 20yrs

krbyxtrm

3 20yrs krbyxtrm

Running Xilinx and Altera Tools on Fedora Core 5

Both Xilinx and Altera make the assumption that their tools are being run on a ridiculously obsolete versions of Linux....

2 20yrs

bjrosen

2 20yrs bjrosen

Aurora sample design: Testing/Eye Diagrams

Hi All, I have the following issues while trying to test a sample Aurora core. I generated a core w/ the following spec...

2 20yrs

bkamakot

2 20yrs bkamakot

OVERCOAT - FPGA Development Arrays

For those that have asked about our Overcoat option to generate FPGA arrays there is now a page on our site at http://w...

0 20yrs

removethisthenleavejea

0 20yrs removethisthenleavejea

reverse from jedec to abel

I have some very old jedecs for a 22v10 that I would like to back compile into abel logic equation files. Any ideas ? Th...

0 20yrs

edbroughton

0 20yrs edbroughton

generating IP cores

Hi, I've written the code for an application using Xilinx 7.1 . Can I create an IP core out of it? Thanks and Regards, S...

6 20yrs

bj.srikanth

6 20yrs bj.srikanth

Mains pick-up on I/O pins

Hello, I am trying to program an RC-100 demo board, which contains a Spartan-II chip. The board is supposed to send thr...

4 20yrs

m_oylulan

4 20yrs m_oylulan

Power Up delay in FPGA !!!!!

Iam currently working on carbus project.I am really concerned with power delay factor in FPGA's especially Xilinx FPGA'...

2 20yrs

jpvarkey

2 20yrs jpvarkey

PCI Header types !!!

Could somebody give me the format of type 1 and type 2 configuration headers.

6 20yrs

jpvarkey

6 20yrs jpvarkey

Personalization of Xilinx ISE

Hi all, Is there a method for personalization of ISE? One of the personalizations: - For avoiding students to make erro...

5 20yrs

taileb.mehdi

5 20yrs taileb.mehdi

IOB IO Standards in Spartan 3

What if I configure some IOB tu use a standard of 1.8v but vcco 3.8v? Will the FPGA be burned? Thanks in advace for answ...

4 20yrs

taileb.mehdi

4 20yrs taileb.mehdi

System Generator cc1 error

Hi, I am trying to use System Generator but it always shows the following error no matter what type of blocks are used....

1 20yrs

kishore2k4

1 20yrs kishore2k4

hard disk drivers problem

I am writing a interface about the ata interface but I have a problem that the dma request signal is sometimes always h...

2 20yrs

bjzhangwn

2 20yrs bjzhangwn

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