Field-Programmable Gate Arrays

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Need help reattaching top to FPGA

We had the top pop off of a VirtexII-Pro 2vp70 (1704BGA) and need to reattach it. The board and FPGA work fine. For som...
3 comments posted 20yrs
posted by mdini
3 comments posted 20yrs posted by mdini

PCI Design

hi, what is the difference for designing a PCI card for a desktop motherboard and with a Single Board Computer(SBC)? sho...
3 comments posted 20yrs
posted by krbyxtrm
3 comments posted 20yrs posted by krbyxtrm

Running Xilinx and Altera Tools on Fedora Core 5

Both Xilinx and Altera make the assumption that their tools are being run on a ridiculously obsolete versions of Linux....
2 comments posted 20yrs
posted by bjrosen
2 comments posted 20yrs posted by bjrosen

Aurora sample design: Testing/Eye Diagrams

Hi All, I have the following issues while trying to test a sample Aurora core. I generated a core w/ the following spec...
2 comments posted 20yrs
posted by bkamakot
2 comments posted 20yrs posted by bkamakot

OVERCOAT - FPGA Development Arrays

For those that have asked about our Overcoat option to generate FPGA arrays there is now a page on our site at http://w...
0 comments posted 20yrs
posted by removethisthenleavejea
0 comments posted 20yrs posted by removethisthenleavejea

reverse from jedec to abel

I have some very old jedecs for a 22v10 that I would like to back compile into abel logic equation files. Any ideas ? Th...
0 comments posted 20yrs
posted by edbroughton
0 comments posted 20yrs posted by edbroughton

generating IP cores

Hi, I've written the code for an application using Xilinx 7.1 . Can I create an IP core out of it? Thanks and Regards, S...
6 comments posted 20yrs
posted by bj.srikanth
6 comments posted 20yrs posted by bj.srikanth

Mains pick-up on I/O pins

Hello, I am trying to program an RC-100 demo board, which contains a Spartan-II chip. The board is supposed to send thr...
4 comments posted 20yrs
posted by m_oylulan
4 comments posted 20yrs posted by m_oylulan

Power Up delay in FPGA !!!!!

Iam currently working on carbus project.I am really concerned with power delay factor in FPGA's especially Xilinx FPGA'...
2 comments posted 20yrs
posted by jpvarkey
2 comments posted 20yrs posted by jpvarkey

PCI Header types !!!

Could somebody give me the format of type 1 and type 2 configuration headers.
6 comments posted 20yrs
posted by jpvarkey
6 comments posted 20yrs posted by jpvarkey

Personalization of Xilinx ISE

Hi all, Is there a method for personalization of ISE? One of the personalizations: - For avoiding students to make erro...
5 comments posted 20yrs
posted by taileb.mehdi
5 comments posted 20yrs posted by taileb.mehdi

IOB IO Standards in Spartan 3

What if I configure some IOB tu use a standard of 1.8v but vcco 3.8v? Will the FPGA be burned? Thanks in advace for answ...
4 comments posted 20yrs
posted by taileb.mehdi
4 comments posted 20yrs posted by taileb.mehdi

System Generator cc1 error

Hi, I am trying to use System Generator but it always shows the following error no matter what type of blocks are used....
1 comments posted 20yrs
posted by kishore2k4
1 comments posted 20yrs posted by kishore2k4

hard disk drivers problem

I am writing a interface about the ata interface but I have a problem that the dma request signal is sometimes always h...
2 comments posted 20yrs
posted by bjzhangwn
2 comments posted 20yrs posted by bjzhangwn