Hi All,
I have the following issues while trying to test a sample Aurora core. I generated a core w/ the following specs: HDL: Verilog, Lane: 1, Lane Width: 2, Interface: Streaming, Upper MGT Clock: BREF_CLK, Upper MGT clock on GT_X0Y1 (from ucf file, corresponds to MGT4 for a ML321 board)
After using xilperl to compile the design files, I simulated it using Modelsim, and uploaded the bit file using Impact to the board.
I'm trying to test the core by feeding a 3.125Gbps (default data rate based on onboard oscillator) PRBS signal onto MGT4(RXP & RXN). I test the output signal from MGT4(TXP & TXN) by connecting it(TX ports)to a oscilloscope and/or spectrum analyzer. Ideally, you would expect the protocol to simply transmit that data that it received at the RX ports, but the protocol fails to do that. I get an extremely weak signal on the spectrum analyzer and bad eye on the scope. I also tried feeding in a clock signal of 50MHz into BREF_CLK and testing the setup w/ 1Gbps PRBS signal, but that didnt work either.
Can you tell me where I might be going wrong?
Thanks, Billu