Iam currently working on carbus project.I am really concerned with power delay factor in FPGA's especially Xilinx FPGA's .Will that create a problem for cardbus.Could somebody explain on, what all factors will affect the power up delay in SRAM based FPGA's.
The amount of bytes to be transferred from the flash and their datarate.
Rene
-- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net
As well as
- The delay prior to starting up the FPGA download.
- The delay after all of the data has been downloaded to the FPGA while you're waiting for the FPGA to switch into a 'user' mode (typically though this is pretty small).
KJ
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