Field-Programmable Gate Arrays

clockless arbiters on fpgas?

I've been having a really hard time coming up with a design for a robust clockless arbiter in an FPGA, and was wonderin...

23 comments posted 20yrs

posted by megacz

23 comments posted 20yrs posted by megacz

SystemVeriling Synthesis for Xilinx FPGAs

I really wish I could use SystemVerilog to develop RTL in ISE. Do any of the Xilinx folks around know if there there ar...

2 comments posted 20yrs

posted by lvalenty

2 comments posted 20yrs posted by lvalenty

controlling synthesis and implemention with tcl/tk scripts

hi all. i'm trying to set up a tcl/tk script to control my synthesis and implementation (synplify pro / xilinx ise 6.3)...

0 comments posted 20yrs

posted by ed.agunos

0 comments posted 20yrs posted by ed.agunos

How many of the old reference sites are still around?

I was going through my bookmark files(maintained since 6-7 years ago) and found that most of the sites that I used to f...

0 comments posted 20yrs

posted by junk.dontsend

0 comments posted 20yrs posted by junk.dontsend

Using part of CPLD to Invert Own Clock

Hi, Apologies upfront if this is a really basic question, as I am rather new to CPLDs. We have a 0-5V squarewave (appro...

2 comments posted 20yrs

posted by me

2 comments posted 20yrs posted by me

Academic scholarships and training on how to program FPGAs

The course introduces you in the arts of algorithm design under this new paradigm, and gives you the tools to attack se...

0 comments posted 20yrs

posted by jotaandres

0 comments posted 20yrs posted by jotaandres

Virtex-4FX12MM: Any hardware MAC address accessable?

Hi all, my hardware guys are on vacation but I need to clarify this: The EDK soft cores like opb_ethernetlite need the...

9 comments posted 20yrs

posted by henryk.mueller

9 comments posted 20yrs posted by henryk.mueller

combining state machines.

is there a standard way to combine state machines so that recurring tasks are implemented as a seperate machine and call...

3 comments posted 20yrs

posted by manusha

3 comments posted 20yrs posted by manusha

Configuring Spartan 3

I'm having trouble configuring a Spartan 3 in parallel slave mode. The mode pins are set with M0 tied to GND and M1,M2...

4 comments posted 20yrs

posted by spamgoeshere4

4 comments posted 20yrs posted by spamgoeshere4

Price history?

Anyone have info on what fpga/cpld costed at different points in time and their capacity ..?

0 comments posted 20yrs

posted by pbdelete

0 comments posted 20yrs posted by pbdelete

RocketIO signal polarity swap

I'm planning on using the TXPOLARITY and RXPOLARITY attributes in the RIOs on a Virtex-II Pro device (via Aurora cores)...

4 comments posted 20yrs

posted by enquiries

4 comments posted 20yrs posted by enquiries

Problems simulation plb_gemac core for Virtex-II Pro

Hey there, I'm trying to simulate a design generated with EDK 7.1 that uses the plb_gemac core (version 1.01.a). When I...

0 comments posted 20yrs

posted by mdales

0 comments posted 20yrs posted by mdales

Cardbus Power On Reset !!!!!!!!

Could anyone tell me,how much time cardbus reset CRST# signal will be asserted after power signal becomes good.

8 comments posted 20yrs

posted by jpvarkey

8 comments posted 20yrs posted by jpvarkey

How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?

My task is to scale up a 9-bit data by 17/sqrt(21) (= 3.7097), with the best precision possible. Without considering cl...

460 comments posted 20yrs

posted by Mr. Ken

460 comments posted 20yrs posted by Mr. Ken

PLB transfers: PPC to IP

I have a piece of IP that acts as a slave on the PLB. I would like writes to this IP to be 64bits, while reads from it...

1 comments posted 20yrs

posted by joeylrios

1 comments posted 20yrs posted by joeylrios