I've been having a really hard time coming up with a design for a robust clockless arbiter in an FPGA, and was wondering if anybody here can provide input. By robust, I mean that it works correctly with probability=1 and its output never glitches, but may take an unbounded amount of time to resolve.
Charles Seitz describes a solution in custom VLSI on page 260 of Mead and Conway's _Introduction to VLSI Systems_, but this assumes you have control over gate threshholds and can make some of them substantially higher than others.
The basic component that causes problems is the "interlock", a module with two inputs A,B and two outputs X,Y.+---------------+ A -----> | | -----> X | Interlock | B -----> | | -----> Y +---------------+
All signals start low. If A+ (A rises) before B+, then X+. If B+ before A+, then Y+. Once one of the outputs rises, the other one will not rise until the device is reset (assume some sort of reset signal). The important part here is that the interlock can take as long as it likes to raise one of the outputs, but it must raise exactly one of them, and cannot lower it once raised (ie no glitching).
I'm working with Atmel FPGAs, but advice based on other devices would be just as helpful. I thought of using the "internal feedback line" to feed one of the 3-LUT's outputs back into one of its inputs as half of an interlock -- the state of the feedback line being used to determine if signal A+ has already arrived. But the problem is that you might have A+ arrive, which causes the output of the 3-LUT to transition, but then B+ might arrive *before* the LUT's output transition arrives back at the third input to the LUT.
Any pointers? I've come across a rather depressing paper concluding that this isn't possible on the (extremely old) XC4000, but I'm sort of hoping against hope that things may have changed:
This paper claims to have a solution, but doesn't go into detail, so I suspect that they may be overlooking something.
Thanks for any pointers...