I really wish I could use SystemVerilog to develop RTL in ISE. Do any of the Xilinx folks around know if there there are any plans for this? I've been using SV for some time now and like it much more than either VHDL or plain old Verilog. If there was a beta tester program I would love to use it and file bug reports.
-Luke
So I just noticed I wrote "SystemVeriling"...of course I meant SystemVerilog. ;)
Luke wrote:
Mentor's Precision RTL support a subset (including interfaces) of SV, I am not sure if there are any others (I am a VHDL person :-)
You can ask them for a 30 day evaluation license,
Hans
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