Falk Brunner ( firstname.lastname@example.org) wrote: : Alexander Werger schrieb: : > Hi, : > in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 : > device the maximum frequency is about 110 MHz (55MIPS). : > In the Picoblaze product brief : >
: > the performance is 102 MIPS -> 204MHz. : > Anybody has an idea how to increase the maximum frequency on our Picoblaze : > test implementation? Is there any reference implementation for the V4 FX12
: Register the IO-bus. If you dont need access to BRAM via the IO bus, : this will increase clock speed significantly. I remember Picoblaze : reacing ~ 80 MHz in Spartan-3.
I'd second that - the Picoblaze reads IO on the second clock of the instruction so you get one register for free (timingwise). One design I have needs two levels of registers to meet timing and I can afford to compensate for this in the software. (So actually the second level of registers are only there to placate the timing analysis...)
I don't think the scratchpad is in the critical path, but if it is and you're not using it you could try cutting it out.
Looking at page 14 of ug129 the mux between the ALU/INPORT and the register file may be critical, so again if you don't need the scratchpad perhaps using that for IO with direct addressing and removing the INPORT and the downstream mux could speed things up.
An interesting project might be to automate the examination of the assembly file for a design and remval of unused ports / ALU functions etc. and see how much difference it makes.