Field-Programmable Gate Arrays

XIlinx 7.1i ISE problem with Spartan 3e design

Guys/Gals, I am primarily an Altera developer at work, so I have a lot more experience with Quartus than ISE. (our site...

2 comments posted 20yrs

posted by jshamlet

2 comments posted 20yrs posted by jshamlet

Building custom ASIC solutions

Hi All, Not sure if this is the right forum ... please point me if otherwise. I am a hobbyist and making my first foray...

5 comments posted 20yrs

posted by be.geek

5 comments posted 20yrs posted by be.geek

Using version control for Xilinx 8.1i ISE projects and source files

I am using Xilinx ISE 8.1i on Linux. I have a bunch of Verilog and project files that I need to check in to our version...

3 comments posted 20yrs

posted by cairosearch

3 comments posted 20yrs posted by cairosearch

rise/fall clock edge constraint

Hi, If I have a design module port that goes to both rising&falling edge FF, how do I constraint it in FPGA? In ASIC ST...

0 comments posted 20yrs

posted by bcang78

0 comments posted 20yrs posted by bcang78

Ethernet Snooping in the FPGA

Hello, I need to snooping the ethernet data so that corresponding data is send to corresponding link. I mean one input...

4 comments posted 20yrs

posted by praveenkumar.bm

4 comments posted 20yrs posted by praveenkumar.bm

ModelSim: Different SimPrim libraries needed for different Xilinx families?

Hi there, I've just left a computer compiling the SIMPRIM libraries used by ModelSim for Low-Level (post place and rout...

0 comments posted 20yrs

posted by jonathan.a.clarke

0 comments posted 20yrs posted by jonathan.a.clarke

Driving two DCMs with BUFG?

XST doesn't seem to mind that I'm driving two DCMs with a BUFG. Are there any implications of this? I'm using the FX ou...

2 comments posted 20yrs

posted by killerhertz

2 comments posted 20yrs posted by killerhertz

Using ChipScope with EDK flow?

Xilinx gurus, I want to use a ChipScope ILA or 2 in an EDK design. I know I have 2 options for ChipScope: Use the ISE a...

5 comments posted 20yrs

posted by jceven

5 comments posted 20yrs posted by jceven

timings

Hi, I'm working with Spartan3 and ISE 7.1, simulating a small VHDL test program I noted that signal updates within a pr...

4 comments posted 20yrs

posted by marco

4 comments posted 20yrs posted by marco

Xilinx constraining : differential clocks and other details

Hi, For the first time, I'm working with differential clock inputs on the FPGA and I'd like to know how to properly con...

1 comments posted 20yrs

posted by SomeOne

1 comments posted 20yrs posted by SomeOne

is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for

is anyone knew the new version of HWICAP "opb_hwicap_v1_00_c" for virtex-4?? thanks in advance!!!!

1 comments posted 20yrs

posted by zhangxun0501

1 comments posted 20yrs posted by zhangxun0501

Xilinx MapLib:661 errors

Hi, I'm having an abundance of Xilinx MapLib:661 errors. e.g: ERROR:MapLib:661 - LUT4_L symbol "signal" has input signa...

0 comments posted 20yrs

posted by jon

0 comments posted 20yrs posted by jon

DDR SDRAM controller

Hello guys.. Please anyone help me get a ddr sdram controller for the v4lx60 board. Is the Mig tool is enough. thanks in...

0 comments posted 20yrs

posted by subin.82

0 comments posted 20yrs posted by subin.82

Problem with Mig1.5 when used to generate ddr sdram controller

hello guys.. i was trying to generate a ddr sdram controller using the mig tool of xilinx But my problem is the tool sa...

0 comments posted 20yrs

posted by vssumesh_asic

0 comments posted 20yrs posted by vssumesh_asic

Virtex4 FX12 - maximum frequency for Picoblaze

Hi, in a test implementation (ISE 8.1) of a Picoblaze core in a XC4VFX12-10 device the maximum frequency is about 110 M...

4 comments posted 20yrs

posted by awerger

4 comments posted 20yrs posted by awerger