Hi,
I'm having an abundance of Xilinx MapLib:661 errors. e.g:
ERROR:MapLib:661 - LUT4_L symbol "signal" has input signal "signal" which will be trimmed.
There aren't any suggestions in the Xilinx Answers database (at least not listed with that error code). Looking through c.a.fpga, a few people have asked questions about why this is happening and how to fix it (or workaround it), but there weren't any responses, but hopefully someone who had the problem before solved it and is now reading this...
The error seems to change depending on different permuations of "Trim Unconnected Signals", "Preserve Hierarchy on Sub Module" and a few other options, but I can't get it to go away. I'm guessing this is a Xilinx mapper bug, and have filed a web case, but I'm not expecting much via that channel, sadly.
Cheers, Jon