timings

For a functional sim all should change on the rising_edge. Maybe some of your processes are using falling_edge.

-- Mike Treseler

I have no processes working on the falling_edge, just one and working on the rising_edge. I have found that on the simulation of the behavioural model concurrent assignaments done outside the process are done on falling_edges, while during the post-palece-and-route simulation those updates appear on the rising_edge as I expect, any ideas? I can also the small delay of each line of a vector being updated inside the process: if my vector value moves from 0 to 240, I see it changing in the sequence 0 -> 16 -> 48 -> 176 -> 240 (start to end within 0.2ns). I made some experiment changing the placement of the otput pads of those vector bits (putting one for each bank instead of all in one bank) and I found the total time required to change from 0 to 240 to become 0.2ns, with a new sequence 0 -> 64 -> 80 -> 112 ->