hello guys.. i was trying to generate a ddr sdram controller using the mig tool of xilinx But my problem is the tool saying my pin assignment(ucf written looking to the board scematic) are wrong.when i tried to verify using the verify your ucf tab from Mig.
From the board shematic i can see 10 banks but in the mig tool there is
only 9 banks is there is any problem in the mig pin assignments thanks in advance