Looks like I have a few more hurdles before getting started with my Spartan 3e board. This time, I seem to be having trouble generating models with Core Generator.
I am using the Xilinx ISE 7.1i webpack - not sure if that makes a difference of not.
Although I'm not sure if it applies to 7.1i, I read that 8.1i has problems with spaces in the path names, so I made sure to install ISE to a path with no spaces. (C:\MyData\Xilinx\ISE_71i). The Core Generator project is likewise stored in C:\MyData\Xilinx\Coregen. So far, I can do simple builds in pure VHDL with good results (I can even program the bitstream into the target board with impact)
However, trying to create models in coregen results in an exception error for some (I don't ever see the customization screen) and for others, like the FIFO model I need, I get all the way through the process, only to see this:
Customizing IP... Finished Customizing. Generating IP... ERROR:coreutil - IO error when creating files for XST synthesis! ERROR:coreutil - Failure to generate output products Finished Generating.
And some actually seem to work. I can create a distributed memory model perfectly fine: Generating IP... Generating Implementation files. Generating the VHDL wrapper. Generating the VHDL instantiation template. Generating the SYM file. Generating ISE symbol file... Generating NGC file. Finished Generating. Successfully generated dist_mem. Customizing IP... Finished Customizing.
I can also create DCM models as well. I haven't tried everything, but it seems kind of hit&miss.
Any clues? I need a FIFO model for a serial transciever I am porting over from an Altera design. The FIFO is a single clock, 8-bit wide, 512 locations deep, model with almost full & almost empty.
For reference, I have ISE 7.1i (webpack) with SP4 installed, and IP update 3. I have tried both versions of Fifo Generator installed (2.1 and 2.2) and both produce the same errors.
Thanks (again)
-Seth