Hi,
Does anyone know of a way to stop Synplify from pre-pending a "Z" to names of top-level entity I/O signals which begin with an underscore ("_") when generating EDIF?
Thanks.
- Jacob
- posted
17 years ago
Synplify prepending Z's to top level signal names in Verilog
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- Vote on answer
- posted
17 years ago
I tried a few workaround possibilities with no joy. It looks like you're stuck with the Z (or z). \Literals, no. Attribute syn_keep, no. Attribute syn_edif_scalar_format in three flavors, no. IBUF instantiated, no.
Sounds like it's time for an enhancement request! I'd love to know if there
*was* a workaround outside of filtering the edif.- Vote on answer
- posted
17 years ago
Oh well, I guess I'm at the mercy of Synplicity and/or my perl skills.
Thanks for trying though,
- Jacob
John_H wrote:
- Vote on answer
- posted
17 years ago
I've had the same error too, it comes when you have specifyed false path constraints on some of your IO signals.
If using Synplify Pro with the ucf constraint file, a workaround is to use the output ndf file as the input constraint file to the PnR tool. Indeed, the signals renamed in the netlist are also renamed in the ndf file. The modifyed names are then transparent to the PnR tool (at least in Xilinx ngdbuild, map and par).
Personnally I have written a small sed script which changes back the names in the netlist.
H> Oh well, I guess I'm at the mercy of Synplicity and/or my perl skills.