Hi i'm using the Xilinx GSRD design.
Now i try to connect a simple IP core to the reference design. The problem is that i can not connect my IP to the OPB or PLB bus. The 2 PLB Bus controllers supports only 1 Master and 1 Slave and they are alread connected.
The connection over the OPB does not work because they use a DCR2OPB bridge. May be the way over the DCR is a solution? How can i manage this connection. Are there some examples?