Chaos in FF metastability

I would imagine that metastable flip-flops might well be capable of chaotic behaviour but, like you, I didn't find any published reference for this.

Like a "classical" chaotic system such as a double-pendulum, whether any chaotic behaviour actually occurs will depend on the physical parameters and initial conditions of the system. So even if the equations governing the flip-flop's state permit chaotic behaviour, it might never appear under "normal" circumstances.

I am not a semiconductor physicist (I'm not *any* kind of physicist) so I can only speculate! :) Would also be interested to know the answer to this.

-Ben-

Thanks for the interesting question.

Metastablility is a whole lot of different things under one name, with the one thing in common being the output is expected to be digital and the process for getting there is analog.

Some of the TTL FFs have behavior in metastable cases that might well be chaotic. TTL can do all sorts of weird things when metastable, including oscillating. To prove that one of those weird things was both metastable and chaotic could be done if someone could find a period*3 variation in the oscillation after a metastable event.

Standard IC CMOS FFs on the other hand, I don't think so. The internal nodes and output do not oscillate, due to the design, as far as I understand it. No oscillation, no chaos.

One could clearly design a FF in any technology that would have chaotic metastable behavior. Or a larger circuit with chaotic behavior that depended on the metastability characteristics of the FF.

This brings up a different sort of questions:

Would there ever be a reason to design a FF to have chaotic metastable behavior? I can't think of any, but perhaps I'm missing something.

Are there any useful chaotic circuits that depend on the metastability characteristics of one or more FFs?

A google search finds this:

-- Phil Hays (Xilinx, but speaking for himself)

Sounds like an ideal target for experimentation :)

ie build a significant number of cells that you make deliberately metastable, and store the results. I'd do this one-at-a-time, to avoid cell coupling effects. ( ie, if you have 512 cells, use 512 edges to get the results )

Of course, actually hitting the very narrow metastable zone is going to be non trivial. It would need a 'deliberate seeking' circuit design.

Yes and no. They are regenerative, and they are also analog, and there has to be threshold noise in there as well... So there is chaos in the settling time/final value.

If you mean never settle, that would be very hard.

But there is a wide area of usage for seeding random number generators. Some devices use local oscillators for this, but they are power hungry, and less than ideally random.

-jg

When I was so much younger, an elder colleague now retired explained a little experiment he used to do for the new lads that weren't quite sure about metastability, must have been early 70s.

Using classic 4000 series RCA cmos devices, he would set up a flop to go meta stable and keep it there by watching it come out. It needed a servo loop that would put a voltage onto Din with a D/A converter and restore the flop back to the middle state if it came out adjusting the servo to maximize the period. Can't recall how long though. You could probably repeat that today if you could find real 18v style cosmac parts.

John Jakson

I have spent some time in analyzing and measuring metastability. Maybe I can point out some aspects: I usually explain metastability by flicking a sharp pen so that it either tips forward or backwards on the table. There is a very, very small chance of giving it just so much energy that it ends up standing on its tip with zero end-velocity. How long it stays there depends on the mass of the pen, the polar momentum, gravity, and thermal noise. The electrical equivalent is the cross-coupled latch. It might end up in the metastable balanced state, and the duration of the stay depends on the gain-bandwidth product of the latch feedback, plus the system noise. A CMOS latch is very simple, and has much higher gain x bandwidth than the old TTL circuits, which could behave quite badly (oscillating,...) I have measured modern (well, kind of modern: Virtex-2Pro) latches, and I found that they very, very rarely stay in the metastable state longer than 3 ns. To get them to do this requires a very precise timing relationship between the data and the clock input. The capture window is substatially less than a femtosecond, which is a millionth of a nanosecond. I have not found a way to do this in a deterministic way, but it is quite easy to do it statistically, just use lots of asynchronous MHz on clock and data, and capture the rare occurance of en extra delay. See the Xilinx app note XAPP094. These measurements nicely quantify the metastability risk. Now back to Chaos... Peter Alfke

You may use this as an analogy, but it is not mathematically equivalent. The pencil model is not capable of any form of oscillation as it is too simple. But in my original post I explain that something as simple as a damped, driven pendulum *is* capable of chaotic operation. That is why I ask if the "cross-coupled latch" has a similar type of complexity as the pendulum and is capable of chaotic operation.

Two mistakes perhaps? The latch is not equivalent to the pencil and I believe the noise is not a factor in resolving the metastability. This was discussed here once ad nauseum and I never read an explanation that was other than the seat of the pants on why noise would actually help to resolve metastability. Please correct me if I missed something and am wrong about this.

Yes, chaos! The book I read did not give any real math details on the requirements for producing chaos, but there were several very simple examples. They talk about some very simple examples with three "attractors" where any point around the borderline between them is always adjacent to points which will take the system to any of the three states. But with only two attractors, a FF may be too simple a system to show chaos. Good thing we aren't combining metastability with multivalued logic. ;^)

Noise and such isn't chaos, in the mathamatical sense of the term.

-- Phil Hays (Xilinx, but speaking for himself)

Hi Peter, I agree with you, the pen example is rather good. Over the years, people like Xilinx have been making the tip of the pen sharper and sharper. On to chaos: I don't think a system needs oscillation of each component comprising the system in order to be chaotic. The resultant system changing state is the chaotic thing, rather than the FF oscillating. For example :-

In this scenario, each individual doesn't oscillate, they just live or die, but the system is chaotic. Also, what matters is the sensitivity to initial conditions. Again see the previous example. The state of the system has to be dense, but that's possible to build with a logic circuit. e.g. all those computer simulations of Lorenz systems. If you had a lot of pens, and the flick of each one depended on the outcome of the previous pen's flick, I think that could be chaotic, (And not only in the mathematical sense if you use fountain pens!) if the flick impulse each time is very close to the 'metastable' impulse. In conclusion, I think an individual CMOS FF given a single metastable clock event doesn't comprise a chaotic system, but you can make a chaotic system with several of them, no trouble. Cheers, Syms.

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Symon schrieb:

You use different meanings of the word oscillation. Peter meant this with oscillation:

"In mathematics, oscillation is the behaviour of some sequences, or a function, that does not converge, but also does not diverge to +? or -?; that is, oscillation is the failure to have a limit."

With that definition the population example clearly oscillates for all values of r larger than 3.57.

The article you cited state the opposite: "At r = 3.57 (approximately) is the onset of chaos. We can no longer see any oscillations." This comes from a definition of oscillation like this

"Oscillation is the periodic variation,...". I guess that is what you mean with oscillation.

Anyway, you need negative feedback for chaos in a system and the CMOS latch does not have any.

Yes, but in the model. Chaos and noise are different things. If you flip the coin in an identical way (not possible, but thats beside the point) it will always show the same behaviour in the abscense of noise. There is a threshold value. Below the threshold it will flip one way, above it will flip the other way.

A chaotic system would show some complicated pattern close to the threshold without noise. The pencil experiment with added noise will look very similar to that, but that is not what chaos theory is about.

Sure. You can build a CPU out of them an compute the logistic map ;-)

Kolja Sulimma

What feature about the CMOS latch makes it impossible to oscillate? My understanding is that there are two nodes with logic driving them to opposite polarities. If the FF is driven into metastability the two nodes can be driven to the same state which due to the logic, is unstable. since there is a delay from the input to the output of each node, it should be possible for each node to drive the other to the opposite state, then both nodes will be in the other state and drive the other node to the original state, etc. What prevents this in CMOS logic?

Disclaimer: naive understanding exposed herein, without benefit of clear understanding of control theory :-)

Roughly, I think it's because the CMOS latch circuit has only 2 gain stages in its loop, and both of them have delays that are dominated by an RC effect (first-order) and, by comparison, its time delays are negligible. So the whole thing is quite highly damped. By contrast, TTL latch circuits often had rather more gain stages, I think. If you simply cross-couple a pair of bipolar transistors you get an embarrassingly slow circuit; TTL used all kinds of tricks to make it faster - remember that NPN transistors were cheap, but just about any other kind of component on TTL was troublesome to make.

If you use an ordinary digital simulator to model a two-inverter feedback loop, and give each inverter a pure time delay, it's easy to make the thing oscillate by prodding it appropriately. But if the two inverting gain stages have a first-order RC-type lag that swamps their propagation delay, an analog simulation will show the thing settling monotonically after any disturbance from its metastable "balance point".

I'd be *very* pleased to hear any experts explaining, in a way that I can understand both mathematically and intuitively, a more rigorous version. Control theory always pushed the limits of my mathematical competence, and as the math wiring in my head shows an approximately exponential decay with time, it needs to be pretty simple these days if I'm going to follow it...

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TTL flipflops were symmetric master-slave architectures with lots of delay in the positive feedback path. If they did get into serious oscillation, the saturation of various stages effectively reduced positive-feedback loop gain. LSTTL was notorious for metastable oscillations, with hundreds of cycles, lasting microseconds, observed. An FM radio would now and then click when placed near a big LSTTL system. CMOS transmission-gate latches don't have this combination of symmetry and delay, so don't oscillate; the balanced pen is a good analogy.

I've seen ecl flops ring once before resolving, but I don't think they sustain an oscillation either.

John

I use a ball rolling over a speed-bump. It's naturally only one dimensional.

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I'm not convinced by these dynamics analogies. These are just unstable systems in an enery maxima, where a slight perturbation leads to a more stable, lower energy, configuration.

In normal (my normal, anyway) usage of the term 'metastable', what's meant is an asychronous circuit with feedback, in which more than one input changes 'simultaneously', leading to oscillation because of a hazard. In practical circuits, the oscillation is damped and decays.

Ok, in some practical circuits there may not be enough energy involved to actually switch a transistor and it may hold in an intermediate state for a significant time, but this is just a detail. Using this to describe general 'metastability' seems to me to be ignoring the big picture.

Evan

Before you complain, I'm sure you're all quite capable of explaining the big picture as well...

:)

Hi Evan, Not all metastablility manifests itself as an oscillation. e.g. CMOS FFs. In fact a metastable FF doesn't necessarily have to have oscillation or even a 'funny' output voltage. (Imagine a circuit which has a funny output voltage followed by a comparator with large hysteresis) All it must have is an indeterminate clock to output delay. I think you're wise to be unconvinced by dynamics analogies. I agree you need different analogies for different FF technologies, but the pen/speed bump ones are good for what's inside CMOS FFs. Probably! :-) Cheers, Syms. p.s. Just in case you haven't seen it, there some stuff on Philip's website which may be of interest.

I like the ball because the key idea, energy, is so obvious.

It takes energy to change states. You get in trouble when you don't have enough. If the ball is rolling too slowly it won't get over the bump. If the setup/hold times are not met (or the clock pulse isn't clean) you get a runt pulse which doesn't have enough energy to change the state of the FF.

It doesn't take two inputs. You can get metastability with a simple runt pulse into a R/S FF.

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These are analog circuits, so you can always find a way to set a gate input such that an output is neither '0' nor '1'. Is that metastability? This is just semantics, but I would say not; it's just another (uninteresting) way to get an invalid output. Philip Freidin's article (the link posted by Symon) appears to talk exclusively about the multi-input synchronisation version of metastability, which is what I understand the word to mean.

Evan