I want to know the registers state after the configurations(altera)
- posted
17 years ago
register state when power on
Loading thread data ...
- Vote on answer
- posted
17 years ago
Oddly enough your answer is given in any of Altera's FPGA data sheets. Below is a sentence pulled from the Stratix data sheet.
User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistors
on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform
the function assigned in the user's design.