Properties of some pins of Vertex4

Vassili schrieb:

• What is HSWAPEN exactly for

1 HSWAPEN enables(or disables) pullups when FPGA is *NOT* configred. 2 LVDS - the best thing todo is to actually create the design and see if the place and route complains or not. There are many restrictions on the IO Pin useage specially in Virtex-4 so it is VERY hard to figure out what is ok and what is not - as example in FX12 no IOPAD from the right half of the chip can reach any DCM input! Was a big surprise for me!! So read the manual, but better make the design assign pins and check it is routable!

Antti