Field-Programmable Gate Arrays

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Assigning unused pins in Quartus II

Hi folks I have a VHDL design which I'm putting on an FPGA with Quartus II. There is a specific pin on the FPGA which I...
9 comments posted 20yrs
posted by rnbrady
9 comments posted 20yrs posted by rnbrady

Virtex-4 Vicm for LVDS with Vcco = 3.3V.

Hi All, So, it looks like it's OK for me to use an unterminated LVDS input on an I/O bank with Vcco = 3.3V. I even chec...
2 comments posted 20yrs
posted by symon_brewer
2 comments posted 20yrs posted by symon_brewer

Xilinx Virtex-4 APU Controller Questions

Hello all, I am in the process of creating a floating point FCM that interfaces with the APU controller on a ML403 deve...
2 comments posted 20yrs
posted by jarrodjwood
2 comments posted 20yrs posted by jarrodjwood

DLL in spartan2e

Hi,everyone,I now use the spartan2e400,and I want to use the dll in fpga,I need 4 clock in fpga,so I have to divide the...
1 comments posted 20yrs
posted by bjzhangwn
1 comments posted 20yrs posted by bjzhangwn

DIFFICULT MULTICYCLE PATH WITH QUARTUS II

Hallo to everybody, i'm trying to map a very large design onto a stratix EP1S80B956C7 device. After timing analysis wit...
6 comments posted 20yrs
posted by salvatore.callea
6 comments posted 20yrs posted by salvatore.callea

wrapper file error : ports not on the entity

My target board is virtex 4 and I'm trying to simulate multi microblaze processors. I am adding cache controllers to my...
0 comments posted 20yrs
posted by findadiat
0 comments posted 20yrs posted by findadiat

Development Boards -Your chance to suggest features

Following our recent Swinyard1 (Virtex-4) release we are now looking at the Swinyard2 module concept which will be base...
22 comments posted 20yrs
posted by removethisthenleavejea
22 comments posted 20yrs posted by removethisthenleavejea

sopc -apex20ke1500xxxx

hi all i hav a sopc board(with apex20ke1500xxx fpga),altera quartus ii tool, i got a sof file, now the board is having...
0 comments posted 20yrs
posted by nmnaik
0 comments posted 20yrs posted by nmnaik

High-speed DAC/ADC with FPGA

Hi folks I'm working with an Altera Stratix ep1s10 on a development board. The data sheet says the IO can operate at ra...
16 comments posted 20yrs
posted by rnbrady
16 comments posted 20yrs posted by rnbrady

PROM files: build .bin for daisy chain on the fly

Currently we use iMpact to create daisy-chain .bin file for our motherboard populated with plug-in cards, each with its...
3 comments posted 20yrs
posted by jackhab
3 comments posted 20yrs posted by jackhab

LUT4 INIT value to implement 2:1 MUX ?

Hi All, I have searched long enough now with no luck, this should be trivial for someone: In the LUT4 instantiation bel...
8 comments posted 20yrs
posted by peter
8 comments posted 20yrs posted by peter