Field-Programmable Gate Arrays

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LUT4 INIT value to implement 2:1 MUX ?

Hi All, I have searched long enough now with no luck, this should be trivial for someone: In the LUT4 instantiation bel...
8 comments posted 20yrs
posted by peter
8 comments posted 20yrs posted by peter

The FFs with synchronous reset perform worse?

Hi, all: The FFs can be reset synchronously or asynchronously. And in ASIC design, the FFs with asynchronous reset will...
8 comments posted 20yrs
posted by lizhongqi
8 comments posted 20yrs posted by lizhongqi

Weird JTAG lockup issue, where is the BUG?

Hi I have several Spartan3 boards that have a very weird issue, namly when configured with one specific VHDL design usi...
10 comments posted 20yrs
posted by Antti.Lukats
10 comments posted 20yrs posted by Antti.Lukats

SP305- PROM configuration

I have a valid bitstream and it works fine in the FPGA. BUT ! How do I convert this bitstream into a PROM-file and get t...
1 comments posted 20yrs
posted by someone
1 comments posted 20yrs posted by someone

PPC XMK bootloader for ELF files

I'm trying to get a Virtex4 PPC405 boot loader to run an ELF file stored in DRAM. I have setup the PPC to read binaries...
0 comments posted 20yrs
posted by s1r.h3nry
0 comments posted 20yrs posted by s1r.h3nry

Xilinx Xcell Journal received damaged

So I've been on the mailing list for Xilinx's Xcell Journal glossy magazine for a year or two now, and something I've n...
3 comments posted 20yrs
posted by gavin
3 comments posted 20yrs posted by gavin

Timing Error in edk 7.1i

hi all, we are getting the following timing error...........the timing analyser does not show any error ...... Asterisk...
0 comments posted 20yrs
posted by vidyutg
0 comments posted 20yrs posted by vidyutg

Warning issue!!!

Hello! Everybody I got a double port RAM from Xilinx IP core generater. I test it. There is always one warning : No pri...
0 comments posted 20yrs
posted by threeinchnail
0 comments posted 20yrs posted by threeinchnail

FATAL ERROR IN EDK 7.1i

hi all, while generating the bitstream for a design with two processors and ddr sdram i'm getting the following error i...
1 comments posted 20yrs
posted by vidyutg
1 comments posted 20yrs posted by vidyutg

The difference betweeen SLICEM and SLICEL

Hi, all: I know there are some differences between SLICEM and SLICEL, like "only the SLICEM has the RAM feature, SLICEL...
1 comments posted 20yrs
posted by lizhongqi
1 comments posted 20yrs posted by lizhongqi

Virtex4 Mini-Module GBL Phy

Hi, Does anyone has a description of Virtex4 Mini-Module GigaBit LAN Phy (BCM5461) PCS registers? I desperately need th...
2 comments posted 20yrs
posted by ales.gorkic
2 comments posted 20yrs posted by ales.gorkic

PCI IOs, tiofoi, source sampling bypass

The following is taken from a Xilinx Webcase (18292, http://tinyurl.com/hclbc) "My design is a simple circuit with an I...
8 comments posted 20yrs
posted by jean-baptiste.nouvel
8 comments posted 20yrs posted by jean-baptiste.nouvel

recognizing multiple fpga's

Hi All, We have a prototype board with 4 fpga's. One is an XC3S1500 and the others are XC3S200. There are a lot of jump...
0 comments posted 20yrs
posted by subhasri.krishnan
0 comments posted 20yrs posted by subhasri.krishnan