how to implement multi-port memory

we had this topic a few months ago - google this group for "Question about multi write ports RAM in FPGA?"

bye, Michael

I can't help with that other than doing a Google search for you. But I will say that one of the things I have learned from studying programming in Forth is that often when a solution is particularly hard, it can be easier to change the problem.

It is easy to provide more read ports. You just use more memories with common write ports. As long as the memories have been written with the same data reads from all memories will be equvalent. But the multiple write ports is not so easy. If a 4 port write memory is hard to construct, it is possible to instead use 6 - dual port memories to provide individual point to point comms between the four writers? Do they *really* need to all write to the same memory that everyone else is writing to?

Another solution is to share the memory interface the way you would share a bus. But I am sure you have thought of these possibilities. I just thought I would toss them out for reconsideration.

Let's get a difficulty rating from you: how fast do you need to read/write data? Do you ever want to write to the same address with specific port-order priority on who gets the valid write?

Thankyou all for nice comments and pointer.

Each writer (processor), accessed its own address space, point-to-point connection might be better.

I need another comment and pointer. Problem now I have is "how to connect each distributed memory to I/O". Since the input/output data is "streamed" (or serial) in the application I consider, I do not have idea how to "transfer" block of input streamed data to processor-private memory and vice versa. I 've thought of these things, but not yet there --:. Thankyou

Thankyou all for nice comments and pointer.

Each writer (processor), accesses its own address space, so point-to-point (p2p) connection might be better.

I need another comment and pointer. Problem now I have is "how to connect each distributed memory to I/O". Since the input/output data is "streamed" (or serial) in the application I consider, that is,

Input data stream ----> multiple processors and p2p-connected memories

---> Output data stream

I do not have idea how each memory takes data from and to I/O. I 've thought of these things, but not yet there --:. Thankyou for your comment again.

I'm not quite sure what you mean. If you have a piece of shared memory, as soon as one processor writes to an address, the other processor can read it. All you need to do is to make the reader aware that the data is ready to be read.

This can be done by polling or by interrupt. The writer can write the data, then when the data block is complete, write to a location to indicate the data is ready. This location either needs to be a counter so that the reader can uniquely tell when new data has arrived, or it can be a semaphore with the reader clearing the flag once the data has been read and the buffer is again empty. The same shared memory block can support transfers in either direction.

You refer to "streaming" the data to processor-private memory. This sounds more like DMA than it does shared memory. The writing processor writes the data into a private memory buffer and sets up a DMA. The DMA hardware reads the private memory and writes the data to the other processor's private memory. You still need a semaphore of some type to coordinate the transfers and each processor needs to control the address for the DMA. But now each private memory needs to have multiple ports or your DMA has to provide a crossbar to connect all the different ports. This might be much more complicated than the point to point shared memory. It should be a lot easier to just use the intermediate shared memory between each processor pairwise and you only need dual port memory.

If the address spaces do not overlap - why do you need a multi-port memory? If they don't overlap you need n single port memories.

Do you really need to write simultaneously to the memory? Isn't it impossible to block and delay a memory access if one processor writes data?

Some guys say that even the need for a dual-port memory is the sign for a bad designed architecture. Ok - we know that this is not true every time but you should think about if you really need a multi-port memory. (What happens if you have to move your design from the FPGA to an ASIC and dual-port memories are too expensive?)

Ralf