Hi, I am trying to do the post_par simulation of the opercore ddr controller(from opencore.org) There is feedback clk in this design which is said to be routed externally to the ddr_clk. Since i cannot do this in the board i am trying to route it througth the fpga for the maximum delay possible. My problem is whenever i try to route the clock i am getting the error message
"Pack 1569: the dual data rate register i_ddr_sdr/fddrd/u1 failed to join a OLOGIC component as required"
i didnt understand the meaning of this error. I tried to generate extra clk(similar to ddr_clk using the fddrrse) but the getting the same error. regards subin