Quite simple question... but I cannot seem to be able to find the answer:
Given a Code Image initially targeted for a Stratix EP1S40F780C8 - i.e. Speed Grade "-8" - would it then be without troubles to load and run that Image on the corresponding "-6" device...?
The need for the question arises in the crossfire of device availability and the wish of having only one Coding Image to update.
If the design is fully synchronous then there should be no problems, bearing in mind Altera's oddball numbering system where the higher the part suffix the slower the part.
However if you have any dodgy asynchronous behaviour included in the design which relies on things having certain prop. delays to work then definatley not - but you didn't design/verify it like that - did you?
You also need to check out the significance of the 'I' and 'C' (industrial and commercial) speedgrades and verify that your substitute part is indeed faster over your desired operational temp. range.
If the -6 parts don't work, your -8 parts might not work reliably, either. Perhaps this isn't obvious, so let me explain.
As a rule, FPGA vendors use the very same die design for every speed grade. They make a bunch of wafers, test each part for functionality and speed, then separate the working parts according to speed grade.
But suppose the vendor has the bad luck to have a lot of slow-speed part orders sitting around, but happens to have a surplus of fast-speed parts on hand. It wouldn't be practical to keep cranking out wafers until they get some slower parts, because there's no telling when they'll get them. Murphy says that when you want slow, you get fast.
So what digital parts vendors do, almost without exception, is spec their parts so that the faster speed grade parts can be substituted for lower-speed parts in a pinch. If you're ordering slow-grade parts, there's absolutely no guarantee that the vendor hasn't marked some fast-grade parts with the slower speed grade number and sent them to you.
Of course, the vendor has to guarantee that all faster parts meet the specs for the slower parts. This is done through careful specmanship. For example, take a look at the Stratix AC specs for I/O clock-to-output times: all speed grades have the same minimum spec (at least from what I can tell from a brief perusal of the data sheet). This is important, because if you calculated external hold time margins based on a long minimum clock-to-Q, then substituted a part with a faster clock-to-Q, you could get into trouble. But as long as the vendor has been smart about choosing specs, remarking a faster part as a slower one is all perfectly above-board and legal.
And has been pointed out by others, all of this is moot if you're not using solid synchronous design techniques.
Faster speed grade parts will work in almost all scenarios. While min timing analysis should be conducted to ensure there are no timing problems, likelihood is extremely high that faster speed grade parts will work. To do min timing analysis from the UI use Processing->Start->Start Timing Analyzer (Fast Timing Model).
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