I have a project where I will have a large array of V4 FPGAs. Each chip is intended to connect to its four orthogonal neighbors with no intervening logic. I would like the number of bus connections between chips in any direction in the array to be 150 (600 total I/O per chip). The connections will be bi-directional. The distance between chips will be the minimum I can have with sockets, heat sinks (with individual fans), good layout and noise control. Some of the lines, what ever is necessary, will be used for clock and framing for the bus data signals. I would like to use DDR. During bus transfers, all the lines on opposite sides of the chip will be operating and the other two sides will be quiescent. I'm hoping for a bus clock of 150 MHz.
Comments? ;=)
Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics