Virtex 4, LVDS I/O: Sanity check please

Jul 17, 2006 1 Replies

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I have a project where I will have a large array of V4 FPGAs. Each chip is intended to connect to its four orthogonal neighbors with no intervening logic. I would like the number of bus connections between chips in any direction in the array to be 150 (600 total I/O per chip). The connections will be bi-directional. The distance between chips will be the minimum I can have with sockets, heat sinks (with individual fans), good layout and noise control. Some of the lines, what ever is necessary, will be used for clock and framing for the bus data signals. I would like to use DDR. During bus transfers, all the lines on opposite sides of the chip will be operating and the other two sides will be quiescent. I'm hoping for a bus clock of 150 MHz.

Comments? ;=)

Marco ________________________ Marc Reinig UCO/Lick Observatory Laboratory for Adaptive Optics

Standards like SSTL are good for this due to the low signal swing. The biggest decision is if to use DCI which burns more power in the V4 or to use external resistors which take board area and make routing more difficult.

The other decision is weither you use source synchronous clocking or a common clock approach. At 150 Mhz the common clock is slightly marginal depending on how long tracks are, speed grade, etc. unless you use some DCM based techniques. You can generate a clock that is offset from the common clock a little by using a DCM and use that as clock for register input to gain more time. Alternatively you can use a DCM to null out the clock to output time and get more margin from that.

John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board.

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Virtex 4, LVDS I/O: Sanity check please

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