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In a function, how to I do bit-extension on temp variables:

Here is my function, which does some custom-made multipliers/division. NCVerilog simulations for RTL so far shows no problem but design compiler complains of this warning.

"Warning: myfile.v:276: Variable 'result' may be read before being assigned; the synthesized result may not match simulations. (ELAB-391)"

How do I fix this problem?

function [17:0] mult_ck34; // Multiplication for ck3, cl4 input [14:0] sum_row; input [2:0] multpl_sel; reg [22:0] result; begin case (multpl_sel) 3'b001, 3'b110: begin // 32 + 8 + 2 + 1 // X43>>3 result[20:0] = {{ {sum_row[14]}}, {sum_row}, {5'b0}} + // 32 {{3{sum_row[14]}}, {sum_row}, {3'b0}} + // 8 {{5{sum_row[14]}}, {sum_row}, {1'b0}} + // 2 {{6{sum_row[14]}}, {sum_row}}; // 1 result[22:21] = {2{result[20]}}; end ... ... endcase end

mult_ck34 = result[21:4];

endfunction

Reply to
Mr. Ken
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I'm just guessing, but it may be complaining about the fact that if multpl_sel takes on any values other 1 or 6 at runtime, result[] will not get set.

-- Ron

Reply to
Ron

Thank you Ron, but the case statement has its default, which sets result[] to 23'd0. Thus I suspect it's caused by the bit-extension statement. How can I code it to avoid this loop and with a neat one-liner statement.

result[22:21] = {2{result[20]}};

Reply to
Mr. Ken

I'd take the bit extension out of the case statement, as follows:

mult_ck34 = {result[20], result[20:4]};

Rob

Reply to
RobJ

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