Problems compiling with ISE Webpack 8.2.01i

Hello Freinds. I am a newcomer to the field of programmable logic devices and I am currently trying to teach myself VHDL. I hope to learn some VHDL before the next semester starts. My sole purpose as of now is not to actually synthesise stuff but just to simulate the various designs that I may try to create. I am using the xilinx ISE webpack 8.2 on a windows XP machine. Below I am trying to implement a design called ones_cnt wherein the counter just counts the number of ones in a 4 bit array and prints the result in a binary format.To understand the concept of configuration declarations I have declared multiple architectures and I am trying to use the configuration declaration statement to select one the them.

Heres my code. Its a lil big may be but I hope you guys would have a look.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ones_cnt is Port ( A : in STD_LOGIC_VECTOR (2 downto 0); C : out STD_LOGIC_VECTOR (1 downto 0)); end ones_cnt;

architecture Algorithmic of ones_cnt is begin process(A) variable NUM: INTEGER range 0 to 3; begin NUM := 0; for I in 0 to 2 loop if A(I) = '1' then NUM := NUM + 1; end if; end loop; case NUM is when 0 => C C C C

Reply to
aijazbaig1
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If you want just simulate VHDL, try Active HDL:

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It has a much better user interface and debugging capabilities than ISE and they sell an inexpensive student edition.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

Hello Frank. Thanks a lot for the advice. I would certainly try using the active HDL. Furthermore, I would appreciate if you look at my code and let me know if there is anything wrong with the semantics and/or the syntax or the design flow or anything. Is it just that I can't ISE to work with it?

And is active HDL an all inclusive package? I mean do I need to have separate software packages to generate waveform testbenches and VHDL testbenches?

H> snipped-for-privacy@gmail.com wrote:

Reply to
aijazbaig1

Take a look at the VHDL handbook:

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On page 23 it says "The libraries WORK and STD and also the package STD.STANDARD are always accessible.". So looks like you don't need to "use" it.

Sometimes useful, too: EBNF of VHDL:

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I can't reproduce your error message, but there are lots of little errors, like wrong port names, missing semicolon, incomplete port mappings etc. And looks like you can't use "port map (not actual_part)", but you have to use a signal to invert it and to connect it to another port.

Another important thing, if you want to be portable: Don't use "IEEE.STD_LOGIC_ARITH.ALL", because it is NOT standard:

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Yes, all inclusive:

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--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de
Reply to
Frank Buss

Hi Aijaz, I tried but I can't reproduce the error. Can you zip your project and send it to me? I am nowadays studying VHDL as well and I have some VHDL expert colleagues here.

Wayne

Reply to
quickwayne

Reply to
aijazbaig1

I don't know where the library name isim_temp came from. Did you specify that somewhere? The default name is normally "work" and it is generally best to leave it that way.

If you really want to use a different name for some reason, then in the line above that generates the error, you would want to change it to: use isim_temp.all;

As mentioned, generally you always want to compile entities into a directory named work. There is certainly no reason for a beginner to do differently. Then, if the entities you are using are part of the current project, the "use work.all;" will get them fine.

If you also want to use entities that were compiled elsewhere, that is libraries, then you will have a file that provides a mapping. In Modelsim, the file is named modelsim.ini, or project_name.mpf. I don't know about the simulator you are using, but if it is not Modelsim, it will have some similar process. There, it will map a library name used in the current directory to the work directory where your library actually is located: [Library] sse_mezz_lib = ../../sse_mezz/sseio_hdl/work Notice that the library files are also compiled into a directory named work, but it is a work directory in a different location from the current project.

Reply to
Duane Clark

Hello Duane. Thanks for the feedback. I have tried to rewrite the program and correct the errors which were there in the original one.The program here is the same one as before i.e. it counts the number of ones in the bit stream. The only problem im facing now I can't really understand the library inclusion stuff in modelsim. If my physical name differs from the logical name then in the workspace window I actually see two libraries named after them whereas if the names are the same then theres just this one library called work(provided both of them have been called 'work'). Additionally it seems possible to create a working model without having to include it in a project. It is done by creating a directory and mapping the local primary library i.e. work to it which seems a little too strange to me. ...so to load those files you have to "load that directory" Heres the code:

library work; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.ALL;

entity ones_cnt is Port ( A : in BIT_VECTOR (2 downto 0); C : out BIT_VECTOR (1 downto 0)); end ones_cnt;

architecture Algorithmic of ones_cnt is begin process(A) variable NUM: INTEGER range 0 to 3; begin NUM := 0; for I in 0 to 2 loop if A(I) = '1' then NUM := NUM + 1; end if; end loop; case NUM is when 0 => C C C C that somewhere? The default name is normally "work" and it is generally

Reply to
aijazbaig1

You can have two or more names refer to the same library. That is not at all uncommon. It should work fine.

I am not completely sure what you mean here. You mean that you are putting a library mapping for work in the [Library] section of the project? The mapping of the current work library is implied (assuming you named the directory "work"), so there is no need to put a mapping in the Modelsim ini file, and I would suggest not doing so. But if you put the work directory somewhere else, then the logical mapping in the Modelsim ini file should enough. I don't really know what you mean by "loading" a directory.

Reply to
Duane Clark

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