Hello Freinds. I am a newcomer to the field of programmable logic devices and I am currently trying to teach myself VHDL. I hope to learn some VHDL before the next semester starts. My sole purpose as of now is not to actually synthesise stuff but just to simulate the various designs that I may try to create. I am using the xilinx ISE webpack 8.2 on a windows XP machine. Below I am trying to implement a design called ones_cnt wherein the counter just counts the number of ones in a 4 bit array and prints the result in a binary format.To understand the concept of configuration declarations I have declared multiple architectures and I am trying to use the configuration declaration statement to select one the them.
Heres my code. Its a lil big may be but I hope you guys would have a look.
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ones_cnt is Port ( A : in STD_LOGIC_VECTOR (2 downto 0); C : out STD_LOGIC_VECTOR (1 downto 0)); end ones_cnt;
architecture Algorithmic of ones_cnt is begin process(A) variable NUM: INTEGER range 0 to 3; begin NUM := 0; for I in 0 to 2 loop if A(I) = '1' then NUM := NUM + 1; end if; end loop; case NUM is when 0 => C C C C