large data access to SDRAM at fixed frequency

Hi ! I am new in electronique. I want to make an analog acquisition board with an ARM microcontroler ( Samsung S3C44B0x 66MHz) with a 8Mbytes SDRAM and an A/D converter( Analog AD775 ). The sampling rate of the A/D converter is at 30Mhz, and i would like to connect its digital output to the S3c44b0x data bus by using the DMA of the uC. Data sent by the ADC will be wrote to the SDRAM by using the DMA of uC. But the number of sampling can be very large, and the acquisition/transfert occur at a fixed rate (30 Mhz). The acquisition time and transfert to SDRAM can be more than 64ms (refresh time cycle of SDRAM).

So, my question is : is the internal refresh cycle of SDRAM can disturb the data writing by the DMA to the SDRAM ? The ADC send data to the SDRAM through the DMA at a fixed rate during may be 1 or 2 second, and is this process can be stopped/disturbed by the internal refresh process of SDRAM ?

If yes, is there a solution, to manage the two process ( fixed acquisition and SDRAM refresh cycle) ?

Thank you very much.

Reply to
Loading thread data ...

mpierrotb schrieb:

I guess you need a inbetween controller with some amount of buffer (FIFO).

Regards Falk

Reply to
Falk Brunner

I think also the OP might be confused about refreshing SDRAM. Normally rather than refreshing the entire RAM every 64 miliseconds, a single row is refreshed every 15 microseconds (sometimes 7.5 microseconds). This takes only a very small portion of the SDRAM data bandwidth and would not require a very deep FIFO. In fact for a streaming application like his, you would normally use a small FIFO anyway to gather up a burst's worth of data before writing to the SDRAM. 30 MHz is very slow compared to the available data bandwidth of the SDRAM (even single data rate RAM) so the length of the DMA would not affect the required FIFO depth either.

He could also "cheat" if using single data-rate RAM's and not refresh during DMA. His assertion that the 2 seconds of burst length exceeds the refresh period ignores the fact that the RAM is refreshed by the DMA access itself. This would not be the case with DDR memory, which requires regular refreshing to provide its internal DLL a chance to update (per the JEDEC spec., not all chips actually do this...).

Reply to

Im am not sure if it might help you, but sometimes one might have success with partly blocked writing processes if you run them on higher speeds than the acquisition. Could you try to maintain a 33MHz speed to access the RAM?

Data could be fetched from a ring buffer fed at 30Meg from the ADC interface.

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.