Field-Programmable Gate Arrays

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Verilog case statements

While reviewing the code that the FPGA group has produced, I saw something that looks bad. It is not likely to affect t...
18 comments posted 20yrs
posted by spamgoeshere4
18 comments posted 20yrs posted by spamgoeshere4

4VSX35 LOC placements?

Hi, How does one find the legal values where "things" can be placed? Is it me or is the Xilinx documentation distinctly...
3 comments posted 20yrs
posted by ba
3 comments posted 20yrs posted by ba

Spartan3 5V PCI

Hi, I have a Working Universal PCI Evaluation Kit (Spartan3) without any Bus Switches/resistors etc. The package name i...
3 comments posted 20yrs
posted by yy7d6
3 comments posted 20yrs posted by yy7d6

Does MAC FIR filter need special care?

Hi everyone, I am currently trying to implement a polyphase decimation filter by using core generator in ISE 7.1 The fi...
6 comments posted 20yrs
posted by joy.li
6 comments posted 20yrs posted by joy.li

Wanted: CPU config register code generator

PROBLEM: CPU memory bus is routed into FPGA, where memory-mapped registers are needed for accessing soft perhipherals....
1 comments posted 20yrs
posted by urbpublic
1 comments posted 20yrs posted by urbpublic

Rocket IO as a high speed sampler

Hi everyone, (especially those Xilinx chaps) :-) I've been having an interesting debate with a colleague here, regardin...
12 comments posted 20yrs
posted by benjamin.toddREMOVEALLCAPITALS
12 comments posted 20yrs posted by benjamin.toddREMOVEALLCAPITALS

Guided MAP/PAR in ISE

Hi all, I was wondering if anyone had succeded in saving time by using guided MAP/PAR. I personally find that every tim...
12 comments posted 20yrs
posted by mbmsv
12 comments posted 20yrs posted by mbmsv

IOBDELAY and DCM

Hello, I have a design with two FPGAs (Xilinx Spartan3). Both use common clock, and both can send data to the other one...
4 comments posted 20yrs
posted by r_p_u_d_l_i_k
4 comments posted 20yrs posted by r_p_u_d_l_i_k

EDK : *.bit and *.elf Files

Hello I?m working with the EDK and now I have got a question. At the moment I download the Hardware with the EDK and th...
11 comments posted 20yrs
posted by Emperor_
11 comments posted 20yrs posted by Emperor_

Hold violation in Virtex 4

Hi everyone: I'm new to FPGA design (have always worked with ASIC before.) I'm working with Virtex 4, and from time to...
5 comments posted 20yrs
posted by tramie_tran
5 comments posted 20yrs posted by tramie_tran

How to phase align a 10MHz clock using V4LX60 DCM

Hello, I am now working with new board based on ARM processor which is pluged on top of V4LX60 based board from avnet....
4 comments posted 20yrs
posted by subin.82
4 comments posted 20yrs posted by subin.82

Spartan 3 clock to output tristate timing

I've got a problem at work where the FPGA group is at war with the hardware group and I am sick and tired of ducking th...
8 comments posted 20yrs
posted by spamgoeshere4
8 comments posted 20yrs posted by spamgoeshere4

uClinux on Virtex-4 Mini-Module

Hi Folks, Does anybody has any experience with uClinux running on Virtex4FX12 (ML403?) in PPC 405 processor. Can the LL...
7 comments posted 20yrs
posted by ales.gorkic
7 comments posted 20yrs posted by ales.gorkic