Latest threads in Field-Programmable Gate Arrays

"This design element is inferred rather than instantiated" (newbie)

As a complete newbie to Verilog and FPGA's, this statement in Xilinx's documentation has me confused. How do I instanti...

8 20yrs

nevo_n

8 20yrs nevo_n

Verilog case statements

While reviewing the code that the FPGA group has produced, I saw something that looks bad. It is not likely to affect t...

18 20yrs

spamgoeshere4

18 20yrs spamgoeshere4

4VSX35 LOC placements?

Hi, How does one find the legal values where "things" can be placed? Is it me or is the Xilinx documentation distinctly...

3 20yrs

ba

3 20yrs ba

Spartan3 5V PCI

Hi, I have a Working Universal PCI Evaluation Kit (Spartan3) without any Bus Switches/resistors etc. The package name i...

3 20yrs

yy7d6

3 20yrs yy7d6

Does MAC FIR filter need special care?

Hi everyone, I am currently trying to implement a polyphase decimation filter by using core generator in ISE 7.1 The fi...

6 20yrs

joy.li

6 20yrs joy.li

OT (2nd try): do you get paid for your travel time?

I recently traveled to another company to try to debug the company's hardware that they were building for us. The hardw...

9 20yrs

vze24h5m

9 20yrs vze24h5m

Wanted: CPU config register code generator

PROBLEM: CPU memory bus is routed into FPGA, where memory-mapped registers are needed for accessing soft perhipherals....

1 20yrs

urbpublic

1 20yrs urbpublic

Rocket IO as a high speed sampler

Hi everyone, (especially those Xilinx chaps) :-) I've been having an interesting debate with a colleague here, regardin...

12 20yrs

benjamin.toddREMOVEALLCAPITALS

12 20yrs benjamin.toddREMOVEALLCAPITALS

Guided MAP/PAR in ISE

Hi all, I was wondering if anyone had succeded in saving time by using guided MAP/PAR. I personally find that every tim...

12 20yrs

mbmsv

12 20yrs mbmsv

IOBDELAY and DCM

Hello, I have a design with two FPGAs (Xilinx Spartan3). Both use common clock, and both can send data to the other one...

4 20yrs

r_p_u_d_l_i_k

4 20yrs r_p_u_d_l_i_k

EDK : .bit and .elf Files

Hello I?m working with the EDK and now I have got a question. At the moment I download the Hardware with the EDK and th...

11 20yrs

Emperor_

11 20yrs Emperor_

Hold violation in Virtex 4

Hi everyone: I'm new to FPGA design (have always worked with ASIC before.) I'm working with Virtex 4, and from time to...

5 20yrs

tramie_tran

5 20yrs tramie_tran

How to phase align a 10MHz clock using V4LX60 DCM

Hello, I am now working with new board based on ARM processor which is pluged on top of V4LX60 based board from avnet....

4 20yrs

subin.82

4 20yrs subin.82

Spartan 3 clock to output tristate timing

I've got a problem at work where the FPGA group is at war with the hardware group and I am sick and tired of ducking th...

8 20yrs

spamgoeshere4

8 20yrs spamgoeshere4

Designing a matrix multpier block using existing xilinx toolbox

hi everyone, for my class project i need to build a model in simulink , using xilinx system generator blocks..which com...

3 20yrs

sirisha.aluru

3 20yrs sirisha.aluru

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