My simulator constantly give me this warning, the reason being that I am unable to predictable the word length of my test vectors, so I defined a 10K array, which is larger than any of the test vector files.
I need to remove this warning so as to make my testing environment look better. How can I suppress this warning ALONE? I have other warnings which I would like not to be suppressed by global NCVerilog settings.
$readmem warning: words in file "./tv/MSG_INPUT_0021_0200_p315.DAT" less than that given by address bounds
Thanks for your idea.