Field-Programmable Gate Arrays

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DCM vs. PLL

Serious question: Does Altera's PLL's offer an advantage (veratility, jitter, etc) over Xilinx's DCM's? I'm to understa...
13 comments posted 19yrs
posted by robnstef
13 comments posted 19yrs posted by robnstef

uclinux on spartan-3e starter kit

hi i am looking for any step by step guide to use uclinux on the starter kit. i try the site:...
13 comments posted 19yrs
posted by aresolimpico
13 comments posted 19yrs posted by aresolimpico

New release of HDLmaker

I've put a new release of HDLmaker on the web, you can get it at http://www.polybus.com/hdlmaker/users_guide/index.htm...
0 comments posted 19yrs
posted by bjrosen
0 comments posted 19yrs posted by bjrosen

Running DDR below the min frequency

This post might not be directly on topic here but I'm hoping that someone else out in FPGA-land might have come across...
6 comments posted 19yrs
posted by rick
6 comments posted 19yrs posted by rick

ISE 8.2i and EDK 8.1i

Okay here's my problem, My company got a dev board from Avnet with a Xilinx Virtex 4 FX12 FPGA on it. So Xilinx sends u...
2 comments posted 19yrs
posted by polkid
2 comments posted 19yrs posted by polkid

Xilinx Virtual Platform

Hi everyone. I was just wondering if someone knew where to find documentation about the Xilinx Virtual Platform. I'm in...
4 comments posted 19yrs
posted by tnt-at-246tNt-dot-com
4 comments posted 19yrs posted by tnt-at-246tNt-dot-com

Xilinx FPGA editor error ISE8.2

Hey, when i run a script through FPGA editor i get the following error: setattr comp c_DDR2_framebuffer_0/c_Ddr2Interfa...
3 comments posted 19yrs
posted by yttrium
3 comments posted 19yrs posted by yttrium

PCIe latency

Hello, Suppose I have a PCIe core in an FPGA on a PCIe card plugged into a modern PC. What read latency should I expect...
2 comments posted 19yrs
posted by jhallen
2 comments posted 19yrs posted by jhallen

Re: Microblaze - Writing to instruction store

snipped-for-privacy@gmail.com schrieb: > I would like to have a control application running out of a LMB BRAM, > that i...
0 comments posted 20yrs
posted by Antti.Lukats
0 comments posted 20yrs posted by Antti.Lukats

Using multi-cycle contraint and simulate it correctly

I am speeding up a design for data processing, where many simple steps are done causing much overhead. Therefore, I try...
3 comments posted 20yrs
posted by fpgaengineerfrankfurt
3 comments posted 20yrs posted by fpgaengineerfrankfurt

Detect failure in Berlekamp algorithm

Hi all, I have implanted a complete Reed Solomon decoder. I used the Berlekamp-Massey algorithm but I don't know how to...
0 comments posted 20yrs
posted by patrick.melet
0 comments posted 20yrs posted by patrick.melet

OFFSET with DCM NET or derived NET?

I have been trying to use an internal clock net in my offset constraint, sourced from a DCM instance. This appears to b...
3 comments posted 20yrs
posted by killerhertz
3 comments posted 20yrs posted by killerhertz