1. Home
  2. Field-Programmable Gate Arrays
  3. Using multi-cycle contraint and simulate it correctly

Using multi-cycle contraint and simulate it correctly

I am speeding up a design for data processing, where many simple steps are done causing much overhead. Therefore, I try to increase the system speed, by eg. inserting some FFs for critical paths but found fitting problems with the multipliers.

My solution, was to parallelize some large (40x40) multiplications and used multi cycle contraints (two clocks) to make it run. Quartus says, it is fine. After using the constraints, I obtain speeds above 150MHz.

Problem: I cannot check this in Modelsim, because the result of the multiplications show up immediately after on clock, which is not the case in reality.

Reply to
alterauser
Loading thread data ...

If you don't want to do a back-annotated, post place&route simulation, you can add delays into the source code for Modelsim. If you add a fixed delay on your multiplier that is longer than one clock cycle but short enough to meet the setup time on the second clock you can test that the behavior of your multicycle design is correct. One caveat, Quartus probably doesn't give you a minimum clock to output on the multiplier, but it's probably safe to assume that it is LESS than one clock cycle. So you really need to test that the behavior is the same whether the clock to output is less than one cycle (as you see in Modelsim with no delay) or more than one cycle but less than two cycles.

HTH, Gabor

Reply to
Gabor

A couple of questions that will help answer your query: Are you using hard or soft multipliers? What are you doing that you need 40 bit factors?

Thanks, Jay

alterauser wrote:

Reply to
kayrock66

a) In this particular case it is for audio at the moment, the data comes with 48bit.

b) currently the embedded MULs are used by Quartus. Obviously, when demanding very high freqs, Quartus even takes more MULS then required, possibly as a result of doublicated hardware to meet the timing reqs. When I do some softer time contraints, less MULs are used, however. (?)

Anyway: I just need that to verify the logial correctness of the delay actions and timing when rejoining the data paths.

Reply to
alterauser

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.