Field-Programmable Gate Arrays

Davies-meyer in VHDL

Hi everybody; I am new in VDHL and crypto also. I would like to implement the Davies-meyer HASH function ( Hi = Emi(Hi-...

0 comments posted 20yrs

posted by bs.addr

0 comments posted 20yrs posted by bs.addr

ALTERA Automotive Graphics Controller Reference Design--drivers

OK. I know this is borderline for this group, but seems the best place I can think of for asking right now. I am very i...

0 comments posted 20yrs

posted by e_s_p_i_a_n_

0 comments posted 20yrs posted by e_s_p_i_a_n_

ISE 8.1: Process "Map" failed

Hi all, I came back from vacation yesterday, and full of ideas I started to work where I left before the holidays. The...

6 comments posted 20yrs

posted by xjohbex

6 comments posted 20yrs posted by xjohbex

Xilinx .002ns timing error

Hello group, I am getting a strange timing error report with numerous requirements of .002ns with the same source and d...

5 comments posted 20yrs

posted by bradsmallridge

5 comments posted 20yrs posted by bradsmallridge

hex format 16 bit?

in quartus II loading a .hex file into 16 bit rom, would it be little endian, or is only low byte filled??

2 comments posted 20yrs

posted by jackokring

2 comments posted 20yrs posted by jackokring

Configuring an Altera Serial Prom/Flash using a 8051 CPU

Hi Has anyone experience with prgramming a serial prom/flash like the EPCS16 using a 8051 compatible uP. It looks like...

1 comments posted 20yrs

posted by handyman

1 comments posted 20yrs posted by handyman

Xilinx EDK 8.2 released

http://www.xilinx.com/ise/embedded/edk82i_whatsnew.htm EDK 8.2 SP1 is also available Antti

0 comments posted 20yrs

posted by Antti.Lukats

0 comments posted 20yrs posted by Antti.Lukats

OpenRISC + DDR

Has anyone hooked in a DDR controller into OpenRISC? Anyone have any comments or suggestions for this task? I have Open...

0 comments posted 20yrs

posted by karrelsj

0 comments posted 20yrs posted by karrelsj

Need some assistance with ISE OFFSET constraint.

I am trying to meet an offset timing constraint, but I'm not sure I understand the timing report. What's the deal with...

3 comments posted 20yrs

posted by killerhertz

3 comments posted 20yrs posted by killerhertz

Newbie frustration

Hi, I work for a small company and we're looking at replacing some of our old designs FPGAs (in this case because of pa...

6 comments posted 20yrs

posted by darius

6 comments posted 20yrs posted by darius

Modelsim SE Simulation

Hi, I use Modelsim SE 6.0 simulator for my projects. My Project is very big and it takes nearly 15 min for compilation....

7 comments posted 20yrs

posted by krishna.janumanchi

7 comments posted 20yrs posted by krishna.janumanchi

The warning of VCC and GND is normal in MAP file?

Hi, I am new to XILINX ISE webpack software. The map file of its "freqm" VHDL example has two warnings (see below) N77...

1 comments posted 20yrs

posted by rxjwg98

1 comments posted 20yrs posted by rxjwg98

CPU design

For implementing the higher level protocols for my Spartan 3E starter kit TCP/IP stack implementation, I plan to use a...

50 comments posted 20yrs

posted by fb

50 comments posted 20yrs posted by fb

ISE/EDK "target pattern contains no `%'"

Grrrrr! Has anyone got ISE 7.1 working with EDK in Windows? Ever seen this error before? I installed ISE/EDK per instru...

2 comments posted 20yrs

posted by zwsdotcom

2 comments posted 20yrs posted by zwsdotcom

Xilinx ML501 availability

Hi with Virtex-4 I did a bad decision, namly I ordered the first board announced as available what was the Avnet-LX25 b...

4 comments posted 20yrs

posted by Antti.Lukats

4 comments posted 20yrs posted by Antti.Lukats