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PCIe latency

Hello,

Suppose I have a PCIe core in an FPGA on a PCIe card plugged into a modern PC. What read latency should I expect? How much time is it from when I submit a request to the PCIe core to read from the PC's main memory to when I get back the first datum from the PCIe core? How does this compare to PCI-X?

We're architecting a new system and trying to get typical FPGA-based PCIe latency values.

Also, we're looking for recommendations for an 8-lane PCIe development/eval card. Which cards are people using?

Thanks

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/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
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Reply to
Joseph H Allen
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Joseph H Allen schrieb:

The bottom line for all PCI variants if you want performance is: DON'T READ.

Not only the PCI standards but also the chipsets are designed around the concept that data is written back by a bus master device.

On some modern mainboards we see something like 10 PCI33 clock cycles between consecutive reads by the processor. Those reads are adjacent assembler instructions in the source code. This means that the chipset one the mainboard thinks really hard about these read accesses and maybe takes a nap inbetween. What we also see is that one 128-bit read instruction is split into two

64-bit read accesses on PCI and PCIe.

Kolja Sulimma

Reply to
Kolja Sulimma

dont know about PCI Express, but in normal PCI reads are INEFFICENT. it easily takes 10 retries (motherboard dependant) before the first dword gets into the device.

Reply to
mahesh

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