Field-Programmable Gate Arrays

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Audio interface in Spartan 3E Starter kit

Hi All, I like to use the Spartan 3E Starter kit as audio capture/playback developping system as it has Linear Technolo...
1 comments posted 19yrs
posted by espzzh
1 comments posted 19yrs posted by espzzh

Unstable output pin?

I'm running a Spartan3E (100e, vq100) with the VHDL below. It's connected to an LED display. The CLOCK_OUT, for some re...
2 comments posted 19yrs
posted by alexmchale
2 comments posted 19yrs posted by alexmchale

MicroFpga = program an FPGA as it would be a MCU !

FPGA is not a MicroController? .=2E.or is it !? MicroFpga makes an FPGA to look like an MCU, and makes it programmable...
20 comments posted 19yrs
posted by Antti.Lukats
20 comments posted 19yrs posted by Antti.Lukats

MPMC2 and MontaVista Linux

Hi, how can I make a MPMC2 and a MontaVista Linux on ML403 from Xilinx work together? Is there a howtoguide for that pro...
2 comments posted 19yrs
posted by erixx
2 comments posted 19yrs posted by erixx

APU disabled after context switch in Xilkernel

Hello, i'm trying to move data between the ppc405-core of a V4FX20 and a microblaze. The ppc and the microblaze are con...
2 comments posted 19yrs
posted by ahofmann
2 comments posted 19yrs posted by ahofmann

Xilinx PowerPC slower than FPGA Design?

Hi everyone, I've build a custom peripheral and now want to insert new Data into my Design via the PowerPC every clock...
11 comments posted 19yrs
posted by peter.kampmann
11 comments posted 19yrs posted by peter.kampmann

i2c,ahb,apb

Hi, I came across these buses i2c ,ahb,apb.What is the difference between them. I dont know about the ahb or apb .just...
7 comments posted 19yrs
posted by vittal.patil
7 comments posted 19yrs posted by vittal.patil

Xilinx System Generator -> Block RAM

Could anybody explain me the algorithm of the generating RAM (ROM) modules by Xilinx System Generator? I need approxima...
0 comments posted 19yrs
posted by aphedorov
0 comments posted 19yrs posted by aphedorov

Tools that support ECO

HI, Can anyone tell me the tools that support ECO (Engineering Change Order).
1 comments posted 19yrs
posted by jesuraj.vinoth
1 comments posted 19yrs posted by jesuraj.vinoth

Lattice .bit file format

Hi, Does anybody know the internal structure of a Lattice .bit file? I do a CPU design including RAM and ROM for the CP...
11 comments posted 19yrs
posted by johannes.hausensteiner
11 comments posted 19yrs posted by johannes.hausensteiner

DDR2 Memory Controller : IOSTANDARD

We had specified IOSTANDARD = DIFF_SSTL18_II_DCI in the UCF file. We got this type of error during place and route for...
11 comments posted 19yrs
posted by czinyan1983
11 comments posted 19yrs posted by czinyan1983

maximum life of FPGA based products ????

hi Manufacturers claim that SRAM based FPGAs can be used in state of the art products and perform well over a long peri...
6 comments posted 19yrs
posted by moazzamhussain
6 comments posted 19yrs posted by moazzamhussain

What is the difference ?

What id the defference between CPLD and FPGA ? Except Speed ?
3 comments posted 19yrs
posted by sadatakhavi.ali
3 comments posted 19yrs posted by sadatakhavi.ali

synchronous clocks

I have a single input clock in my design, and it is used to drive clock enables to the entire design. The clock enables...
5 comments posted 19yrs
posted by szohair
5 comments posted 19yrs posted by szohair