Lattice .bit file format

Johannes Hausensteiner schrieb:

there is a network reference design at lattice website with Z80 cpu a networking stuff, I think it includes some script to update the bt file as well.

Antti

Hi, Thank you for your hint. Unfortunately I am not able to find the mentioned reference design. Can you provide a link? Thanks again,

Johannes

Antti wrote:

Johannes Hausensteiner schrieb:

Antti

Johannes,

Lattice's current software, ispLEVER 6.0 does offer the ability to reinitialize your memory contents without recompiling your design. Using the Memory Initialization tool, accessed from the tools menu, a new, or modified memory file .mem can be written to the designs database file .ncd. After this is done all that needs to be rerun is the 'Generate Bitstream Data' process. This feature is only available for use on memory blocks that are implemented in the devices EBR blocks and created using the software's IPExpress module generation tool.

Kevin schrieb:

is the memory init available from commandline also? the GUI tool is known to exist for some time, the commandline bit file merging is far less documented

Antti

Yes, it can be run via commandline. In the ispLEVER help do a search for 'memedit', this is the memory initialization tool executable. In the search results select 'Running MEMEDIT from the Command Line' to open the MEMEDIT help page.

Kevin

Antti wrote:

I got the following procedure from the mentioned reference design:

%LATTICE_HOME%\ispFPGA\bin\nt\memedit.exe ROMFILE.mem FPGA_PROJECT.ncd MODULE.lpc INSTANTIATION_NAME

%LATTICE_HOME%\ispFPGA\bin\nt\bitgen -w -g RamCfg:Reset FPGA_PROJECT.ncd FPGA_PROJECT.bit FPGA_PROJECT.prf

This takes about 1 minute compared to 8 minutes for the whole FPGA design.

I made a conversion utility which converts from a standard Intel HEX file to the .mem format ('addressed hex'). You can download it from here:

Thanks again for the fast help!

Johannes

Kev> Yes, it can be run via commandline. In the ispLEVER help do a search

Is it just me or are the file extensions, commands and options very similar to the ones used in Xilinx' ISE flow?

/Andreas

Andreas Ehliar schrieb:

no, its not you.

in all file name extensions in both Lattice and Xilinx flows

it is surprising how much similarity there is. what I found surprising was that even the file format that holds the actual location of fuses in the bitstream is inherited from NeoCad, that both by Lattice and Xilinx

Antti

This is not a secret. The neocad people developed both tool sets.