Hi, I came across these buses i2c ,ahb,apb.What is the difference between them. I dont know about the ahb or apb .just started reading about i2c. I have to test the i2c bus in verilog. In i2c bus DUT(design under test) i saw something like wishbone interface or ahb thing.what does it mean .please explain me in detail. or give some links.I am exploring them too. Thanks, Vittal
Hello,
I've never heard of AHB or APB. I've heard about the Wishbone interface for I2C.
Wishbone is basically an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other. The aim is to allow the connection of differing cores to each other inside of a chip. The Wishbone Bus is used by many designs in the OpenCores project.
I'm assuming you got the I2C interface via Opencores.org? I've successfuly used the I2C interface from Opencores.org. Let me know what you are trying to do. If you have any questions about this particular I2C, I'd be more than happy to help you.
-Markus
vits wrote:
i2c is an off-chip serial bus. AHB and APB are on-chip interconnects. AHB & APB are both part of the AMBA standard from ARM.
Cheers, Jon
Hi Vits,
Opencores' files includes a model of an I2C slave device. I used this model to test my modified Opencores' I2C. You connect the data and the clock of the I2C master to the data and clock of the I2C slave. This is where the I2C wires are located.
One thing to note, the provided I2C slave device only has four registers. You can change the I2C slave device to have more than four registers. I thought I'd share this with you, because this one took me by surprise.
Per your question in regards to the Wishbone interface of the I2C cores. The Wishbone interface is a backend interface that is defined by the author of Opencores' I2C. The interface (in this core's case) is used to control what action the I2C master need to do (e.g. send a start, send data, look for acknowledge, etc).
Hope this helps,
-Markus
vits wrote:
Hi Vits,
I tested the I2C master with the testbench. The signals generated were correct. I also implemented the cores in an FPGA. I've managed to use the core to communicate with slave devices using FPGA as the master. So, I do believe that the I2C master is correct.
I didn't use any microprocessor or microcontroller to control the I2C master. Instead, I created a state machine that takes in my instructions and decode it for the I2C master to process. The state machine also waits for the nack/ack signals that the I2C master receives from the slave (this, I noticed, took the longest in hardware).
Hope this helps.
-Markus
vits wrote:
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