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Xilinx PowerPC slower than FPGA Design?

Hi everyone,

I've build a custom peripheral and now want to insert new Data into my Design via the PowerPC every clock cycle.

My Problem is: how to resolve the next clock cycle with the PowerPC? I've read the Tutorial by Richard Griffin, who suggests to set an additional register that counts backwards a given number, to synchronize with your peripheral.

As I want to use the clock cycle for the next input, I set the clock signal to a bit of my output registers (using OPB Bus with User Logic S/W Register Support on Virtex 2 Pro). I now tried to detect the rising and falling edge of the clock by reading from the Register via the _mReadReg(....) command.

But unfortunately, I never get the rising edge of the clock :( The PowerPC, on which the C++ Code that reads the register, runs with

300 Mhz. The synthesis of my custom peripheral told me a Frequency of about 150 Mhz. The custom peripheral is attached to the sys_clk_s.

I assume that the PowerPC should run significantly faster than the peripheral, but it seems that both run with the same clock.

Hope I have described my problem clearly.

Thanks for any help!

Regards, Peter

Reply to
Peter Kampmann
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Peter,

What's the clock speed of your OPB BUS?

I think I know the answer to this, I just don't know how to explain it. I'm a bit new :)

Regards, Kyle

Reply to
Kyle H.

The OPB Bus clock is attached to the sys_clk_s, in Base System Wizard, the Bus Clock Frequency is set to 100 Mhz and cannot be set higher.

So the problem is perhaps, that the Bus is clocked too slow? It seems that I cannot the the Frequency higher, because when using the PowerPC in 300 Mhz mode, I cannot choose any other frequency in the Base System Wizard. When I try to set the clk to the same clock as the PowerPC (proc_clk_s) I get the error that the RS232 won't work with that frequency? Perhaps I have to use the PLB Bus then? Because its a faster peripheral?

Regards, Peter

Kyle H. schrieb:

Reply to
Peter Kampmann

Peter Kampmann schrieb:

this if possible is very tricky. the _only_ part that actually is able to run at 300MHz is the PPC proc hardmacro itself, all the busses can be run at about 100MHz. So whatever peripherals you have they are on 100MHz busses.

there maybe some tricks in V4 like using the FCB bus, or have special peripherals on OCM bus - but thats all rather complicated business.

whatever is on PLB or OPB runs at about 100MHz max speeds.

Antti

Reply to
Antti

Arrgh,

so that means I am not able to detect the clock signal of a peripheral that is faster than 100 Mhz ? So I'll have to search for an option where I can slow down my peripheral. Hope there is such a possibility?

Regards, Peter

Antti schrieb:

Reply to
Peter Kampmann

I've been dancing around this problem as well. Haven't even come close to finding a way around it, as I'm still learning system design, HDL and the software (EDK).

Regards, Kyle

Reply to
Kyle H.

Kyle H. schrieb:

the user IP cores may run at high clock frequencies that no problem at all. but they have to be connected to 100MHz clocked bus, so there peripheral itself must convert betweent the clock domains

Antti

Reply to
Antti

Antti schrieb:

Hmm I don't understand how this can work, can you explain it to me? The Peripheral runs at, say 120 Mhz, the Bus delivers data at 100 Mhz.

Now I need new Data in the peripheral every clock cycle, but I get only new Data at 100 Mhz and the peripheral wants them at 120 Mhz. So that means I have to slow down the clock internally in the fpga design, as described in the "Custom Peripheral Design Guide".

The Bus2IP_Clk is the clock of the OnChip Peripheral Bus? If this is the case, I have to half this clock, then I have 50 Mhz for the Peripheral, 100 Mhz for the Bus and 300 for the PowerPC and then I should be able to detect clock cylces.

Reply to
Peter Kampmann

How many bits is the data? If it's 8 bits, can you gang 4 together to make 32 bit chunks? Or 2 16 bit chunks to make 32?

If your data bandwidth can't fit in the bus capacity, what can you do? Go back to the drawing board.

-Dave

--
David Ashley                http://www.xdr.com/dash
Embedded linux, device drivers, system architecture
Reply to
David Ashley

Is it possible to generate a XXXMHz clock with hardware, and connect the OPB BUS CLK to that pin? Or is the OPB BUS limited at 100MHz?

Regards, Kyle

Reply to
Kyle H.

Kyle H. schrieb:

the OPB (and PLB) bus clocks must be phase aligned on rising edges with the PPC proc clock. So when PPC clock is 300 max bus clock would be 100MHz

Antti

Reply to
Antti

The easiest way would be to have the PPC stuff the data into a FIFO and your hardware design take it out once each clock cycle. That said, I don't believe the buss for the PPC runs at 300 MHz, I think that is just the core processor speed. You might not have enough horsepower in the PPC to keep up with a 150 MHz clock, depending on the processing per sample and size of the data words relative to the bus width.

Reply to
Ray Andraka

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